Keyword : neural algorithm


Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits
Itsuo TAKANAMI Satoru NAKAMURA Tadayoshi HORITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1678-1686
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Configurable Computing and Fault Tolerance
Keyword: 
fault tolerancethree-dimensional mesh arrayself-reconstructionneural algorithmneural circuit
 Summary | Full Text:PDF(940.2KB)

A Built-In Self-Reconstruction Approach for Partitioned Mesh-Arrays Using Neural Algorithm
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8 ; pp. 1160-1167
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Fault Diagnosis/Tolerance
Keyword: 
mesh-arrayfault toleranceself-reconfigurable systemwafer scale integrationneural algorithm
 Summary | Full Text:PDF(557.5KB)