Keyword : network-on-chip

BMM: A Binary Metaheuristic Mapping Algorithm for Mesh-Based Network-on-Chip
Xilu WANG Yongjun SUN Huaxi GU 
Publication:   
Publication Date: 2019/03/01
Vol. E102-D  No. 3 ; pp. 628-631
Type of Manuscript:  LETTER
Category: Fundamentals of Information Systems
Keyword: 
network-on-chip, application mapping, particle swarm algorithm, sine cosine algorithm, 
 Summary | Full Text:PDF(202.1KB)
AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures
Xuan-Tu TRAN Tung NGUYEN Hai-Phong PHAN Duy-Hieu BUI 
Publication:   
Publication Date: 2017/08/01
Vol. E100-A  No. 8 ; pp. 1650-1660
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
network-on-chip, network interface, AMBA eXtensible interface (AXI), 
 Summary | Full Text:PDF(1.7MB)
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip
Akira MOCHIZUKI Hirokatsu SHIRAHAMA Yuma WATANABE Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2304-2311
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Communication for VLSI
Keyword: 
asynchronous communication link, network-on-chip, multiple-valued logic, current-mode, 
 Summary | Full Text:PDF(1MB)
Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters
Takashi MIYAMORI Hui XU Hiroyuki USUI Soichiro HOSODA Toru SANO Kazumasa YAMAMOTO Takeshi KODAKA Nobuhiro NONOGAKI Nau OZAKI Jun TANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 360-368
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
many-core, network-on-chip, VLIW, low power, face detection, H.264, super resolution, 
 Summary | Full Text:PDF(4.2MB)
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
Masashi IMAI Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1914-1925
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
mean time to failure, network-on-chip, multiple processor system, fault diagnosis, pair and swap, 
 Summary | Full Text:PDF(1.5MB)
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
Yohei NAKATA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 523-533
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
network-on-chip, process variation, adaptive circuits, routing algorithm, 
 Summary | Full Text:PDF(2.2MB)
Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip
Yue QIAN Zhonghai LU Wenhua DOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3211-3220
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
delay bounds, performance analysis, network calculus, network-on-chip, 
 Summary | Full Text:PDF(1MB)
Study-Based Error Recovery Scheme for Networks-on-Chip
Depeng JIN Shijun LIN Li SU Lieguang ZENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/11/01
Vol. E92-D  No. 11 ; pp. 2272-2274
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
network-on-chip, system-on-chip, error recovery, 
 Summary | Full Text:PDF(182.8KB)
Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks
Yue QIAN Zhonghai LU Wenhua DOU Qiang DOU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10 ; pp. 1276-1283
Type of Manuscript:  Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
Category: 
Keyword: 
credit-based flow control, performance analysis, network calculus, network-on-chip, 
 Summary | Full Text:PDF(690.4KB)
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/04/01
Vol. E92-D  No. 4 ; pp. 575-583
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
network-on-chip, FPGA, customize, router, 
 Summary | Full Text:PDF(491KB)
Pre-Allocation Based Flow Control Scheme for Networks-On-Chip
Shijun LIN Li SU Haibo SU Depeng JIN Lieguang ZENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3 ; pp. 538-540
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
network-on-chip, system-on-chip, flow control, 
 Summary | Full Text:PDF(125.2KB)
Design a Switch Wrapper for SNA On-Chip-Network
Jiho CHANG Jongsu YI JunSeong KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6 ; pp. 1615-1621
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
switch wrapper, SNA, SNP, AMBA AHB, network-on-chip, 
 Summary | Full Text:PDF(1.6MB)