Keyword : network-on-chip (NoC)

Simple Oblivious Routing Method to Balance Load in Network-on-Chip
Jiao GUAN Jueping CAI Ruilian XIE Yequn WANG Jinzhi LAI 
Publication:   
Publication Date: 2021/10/01
Vol. E104-D  No. 10 ; pp. 1749-1752
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
network-on-chip (NoC), load balancing, oblivious routing, 
 Summary | Full Text:PDF
The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer
Naohisa FUKASE Yasuyuki MIURA Shigeyoshi WATANABE M.M. HAFIZUR RAHMAN 
Publication:   
Publication Date: 2017/10/01
Vol. E100-D  No. 10 ; pp. 2478-2492
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
interconnection network, network-on-chip (NoC), router, multi-port memory, 
 Summary | Full Text:PDF
A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores
Seungju LEE Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/09/01
Vol. E95-A  No. 9 ; pp. 1538-1549
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
network-on-chip (NoC), hybrid NoC algorithm, hierarchical NoC, busmesh NoC (BMNoC), 
 Summary | Full Text:PDF
A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs
Zewen SHI Xiaoyang ZENG Zhiyi YU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7 ; pp. 1386-1397
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
fault-tolerant routing, network-on-chip (NoC), deadlock-free, divide-and-conquer, system partition, 
 Summary | Full Text:PDF
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip
Binzhang FU Yinhe HAN Huawei LI Xiaowei LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/04/01
Vol. E94-D  No. 4 ; pp. 809-821
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
network-on-chip (NoC), fault-tolerant routing, multiple round dimension-order routing, turn model, 
 Summary | Full Text:PDF
Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing
Tomohiro TAKAHASHI Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1598-1604
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
network-on-chip (NoC), delay-insensitive, dual-rail encoding, globally asynchronous locally synchronous (GALS), point-to-point communication, 
 Summary | Full Text:PDF