Keyword : n-detection test

Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits
Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 586-591
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Scan Testing
hybrid BISTn-detection testpartially rotational scanlow-speed tester
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