Keyword : multiplier and accumulator (MAC)

A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition
Tso-Bing JUANG Shen-Fu HSIAO Ming-Yu TSAI Jenq-Shiun JAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1464-1471
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
multipliers, multiplier and accumulator (MAC), partial product compression, final adder partition, arithmetic functional units, datapath generation, 
 Summary | Full Text:PDF
Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures
Naoki MIZUTANI Shogo MURAMATSU Hisakazu KIKUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8 ; pp. 1951-1959
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword: 
digital signal processor (DSP), filter bank, wavelet transform, multiplier and accumulator (MAC), 
 Summary | Full Text:PDF