Keyword : multiple-valued memory cell


CMOS Implementation of a Multiple-Valued Memory Cell Using -Shaped Negative-Resistance Devices
Katsutoshi SAEKI Heisuke NAKASHIMA Yoshifumi SEKINE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Vol. E87-A  No. 4 ; pp. 801-806
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
analogCMOS-shaped negative-resistancemultiple-valued memory cell
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