Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-DNo. 9 ;
pp. 2304-2311 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Communication for VLSI Keyword: asynchronous communication link, network-on-chip, multiple-valued logic, current-mode,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8 ;
pp. 2109-2116 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: pre-emphasis, high-speed interface, multiple-valued logic, equalization, data-dependent jitter,
A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations Noboru TAKAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8 ;
pp. 2040-2047 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: multiple-valued logic, multiple-valued logic circuits, hazard detection, delay model,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8 ;
pp. 2080-2088 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: multiple-valued logic, current-mode circuit, adaptive current control, many-core processor,
Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources Kwang-Jow GANDong-Shong LIANGYan-Wun CHEN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8 ;
pp. 2068-2072 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: multiple-valued logic, negative differential resistance, BiCMOS process,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8 ;
pp. 2073-2079 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: multiple-valued logic, overlap resolution number system, current-mode circuit, weak-inversion region,
Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation Masatomo MIURATakahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-CNo. 4 ;
pp. 589-594 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: crosstalk, signal integrity, differential-pair circuit, multiple-valued logic,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-CNo. 4 ;
pp. 683-691 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: differential-pair circuit, current-mode circuit, multiple-valued logic,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-CNo. 11 ;
pp. 1591-1597 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: differential-pair circuit, current-mode circuit, multiple-valued logic, dynamic logic,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-CNo. 11 ;
pp. 1645-1654 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: datapaths, arithmetic circuits, addition algorithms, number systems, multiple-valued logic,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/08/01 Vol. E86-ANo. 8 ;
pp. 2001-2010 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: multiple-valued logic, signal processor, FPGAs, FIR filters,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/07/01 Vol. E86-ANo. 7 ;
pp. 1876-1884 Type of Manuscript: PAPER Category: Neural Networks and Bioengineering Keyword: multiple-valued logic, learning, MVL algebra, local search, back-propagation,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/06/01 Vol. E86-ANo. 6 ;
pp. 1525-1534 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: multiple-valued logic, static hazard, prime implicants expression,
Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design Masanori NATSUITakafumi AOKITatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/09/01 Vol. E85-ANo. 9 ;
pp. 2061-2071 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and Its Applications) Category: Keyword: multiple-valued logic, arithmetic circuit, evolutionary computation, genetic algorithm (GA),
Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis-- Masanori NATSUITakafumi AOKITatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-ANo. 11 ;
pp. 2808-2810 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Analog Synthesis Keyword: multiple-valued logic, arithmetic circuits, evolutionary computation, genetic algorithm,
Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams Hafiz Md. HASAN BABUTsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/25 Vol. E82-DNo. 5 ;
pp. 949-954 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications) Category: Circuits Keyword: resonant tunneling diode, HEMT, multiple-valued logic, negative differential resistance,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/25 Vol. E79-DNo. 10 ;
pp. 1453-1461 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple-valued logic, fault masking, cellular array and switch cell,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/25 Vol. E77-CNo. 7 ;
pp. 1042-1048 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: multiple-valued logic, dynamic circuits, small latency, cellular array, template matching,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-CNo. 7 ;
pp. 1133-1143 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Multiple-Valued Architectures and Systems Keyword: multiple-valued logic, set-valued logic, parallel processing, frequency multiplexing,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-DNo. 5 ;
pp. 577-585 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Fail-Safe/Fault Tolerant Keyword: fault tolerance, multiple-valued logic, fail-safe, threshold operation, power press control,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-DNo. 5 ;
pp. 533-539 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic and Logic Functions Keyword: fuzzy logic, multiple-valued logic, Kleene-Stone algebras, partial order relation,
54-bit Multiplier Based on Differential-Pair Circuitry