Keyword : multiple-valued hardware algorithm


Prospects of Multiple-Valued VLSI Processors
Takahiro HANYU Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 383-392
Type of Manuscript:  INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
submicron VLSIinterconnection delaymultiple-valued hardware algorithmparallel VLSI processorMVL arithmetic and logic circuits
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