Keyword : multiple-clock


DFT Timing Design Methodology for Logic BIST
Yasuo SATO Motoyuki SATO Koki TSUTSUMIDA Kazumi HATAYAMA Kazuyuki NOMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3049-3055
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
DFTat-speed BISTtiming designmultiple-clock
 Summary | Full Text:PDF

A 600 mW Single Chip MPEG2 Video Decoder
Kiyoshi MIURA Hideki KOYANAGI Hiroshi SUMIHIRO Seiichi EMOTO Nozomu OZAKI Toshiro ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1691-1696
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
MPEG2video decoderlow power dual-port RAMmultiple-clockasynchoronization
 Summary | Full Text:PDF