Keyword : multicore processor

Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler
Yoshitake OKI Yuto ABE Kazuki YAMAMOTO Kohei YAMAMOTO Tomoya SHIRAKAWA Akimasa YOSHIDA Keiji KIMURA Hironori KASAHARA 
Publication:   
Publication Date: 2020/03/01
Vol. E103-C  No. 3 ; pp. 98-109
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
parallelization compiler, local memory management, multicore processor, global address space, data decomposition, 
 Summary | Full Text:PDF
vCanal: Paravirtual Socket Library towards Fast Networking in Virtualized Environment
Dongwoo LEE Changwoo MIN Young IK EOM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Vol. E99-D  No. 2 ; pp. 360-369
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
device virtualization, multicore processor, para-virtual library, concurrent queue, polling-based notification, 
 Summary | Full Text:PDF
A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform
Bei HUANG Kaidi YOU Yun CHEN Zhiyi YU Xiaoyang ZENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12 ; pp. 2939-2947
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword: 
parallel computing, mapping strategies, Reed Solomon decoder, multicore processor, 
 Summary | Full Text:PDF
Scalable Cache-Optimized Concurrent FIFO Queue for Multicore Architectures
Changwoo MIN Hyung Kook JUN Won Tae KIM Young Ik EOM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12 ; pp. 2956-2957
Type of Manuscript:  Special Section LETTER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
FIFO queue, multicore processor, cache-line contention, compare-and-swap, fetch-and-store, 
 Summary | Full Text:PDF
A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS
Xun HE Xin JIN Minghui WANG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2609-2618
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
SIMD, cache coherence, NoC, GMACs, multicore processor, 
 Summary | Full Text:PDF