Keyword : multi-valued logic

A Packet Classifier Based on Prefetching EVMDD (k) Machines
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2243-2252
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
many core, packet classification, decision diagram, multi-valued logic, 
 Summary | Full Text:PDF
11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic
Sun Hong AHN Jeong Beom KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/03/01
Vol. E90-C  No. 3 ; pp. 623-627
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
redundant multi-valued logic, multi-valued logic, demultiplexer, high-speed interface circuit, 
 Summary | Full Text:PDF
Efficient Triadic Generators for Logic Circuits
Grant POGOSYAN Takashi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5 ; pp. 919-924
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Logic and Logic Functions
Keyword: 
multi-valued logic, logic design, generating sets, 
 Summary | Full Text:PDF
Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic
Jing SHEN Koichi TANNO Okihiko ISHIZUKA Zheng TANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5 ; pp. 940-948
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Circuits
Keyword: 
neuron MOS transistor, multi-valued logic, current-mode circuit, current mirror, current comparator, threshold detector, T-gate, integrated circuit, 
 Summary | Full Text:PDF