Keyword : module selection


A Behavioral Synthesis Method with Special Functional Units
Tsuyoshi SADAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1084-1091
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
Behavioral Synthesisschedulingallocationmodule selectionoperation chaining
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A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units
Tsuyoshi SADAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4 ; pp. 792-799
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high-level synthesisschedulingallocationmodule selectionoperation chaininginteger linear programming
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Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification
Masanori HARIYAMA Shigeo YAMADERA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1551-1558
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
automatic synthesisschedulingmodule selectiondata-path designoptimization
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Module Selection Using Manufacturing Information
Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2576-2584
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-level Synthesis
Keyword: 
high-level synthesismodule selectionmanufacturabilityyield
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Register-Transfer Module Selection for Sub-Micron ASIC Design
Vasily G. MOSHNYAGA Yutaka MORI Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 252-255
Type of Manuscript:  Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
Category: 
Keyword: 
module selectionregister-transfer synthesis
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