Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A
No. 12 ;
pp. 3293-3300
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword:
high speed, cell layout synthesis, Boolean Satisfiability, SAT, CMOS logic cell, minimum width, |
