Keyword : min-cut


Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System
Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2208-2219
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dual-vddmin-cutvoltage assignmentlow powertiming constraints
 Summary | Full Text:PDF

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm
Kengo R. AZEGAMI Masato INAGI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/03/01
Vol. E85-A  No. 3 ; pp. 655-663
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
circuit partitionhyper-graph partitionnetwork flowmin-cutintegrated circuit design
 Summary | Full Text:PDF

A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
Chi-Chou KAO Yen-Tai LAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2690-2696
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: FPGA Systhesis
Keyword: 
technology mappingroutabilitymin-cutfield programmable gate array (FPGA)
 Summary | Full Text:PDF

An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut
Kengo R. AZEGAMI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A  No. 5 ; pp. 1301-1308
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
circuit partitionhyper-graph partitionnetwork flowmin-cutintegrated circuit design
 Summary | Full Text:PDF