IEICE Trans

Keyword : microprocessor

Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison Yasutaka MATSUDA Ryota SHIOYA Hideki ANDO
Publication: Publication Date: 2022/02/01 Vol. E105-D No. 2 ; pp. 320-332 Type of Manuscript: PAPER Category: Computer System Keyword: microprocessor, superscalar processor, instruction-level parallelism, issue queue, power consumption,
	Summary \| Full Text:PDF(1.1MB)

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing Koki ISHIDA Masamitsu TANAKA Takatsugu ONO Koji INOUE
Publication: Publication Date: 2018/05/01 Vol. E101-C No. 5 ; pp. 359-369 Type of Manuscript: INVITED PAPER (Special Section on Innovative Superconducting Devices Based on New Physical Phenomena) Category: Keyword: single flux quantum (SFQ), cryogenic computing, microprocessor, cache memory, Josephson junction, low-power, high-performance, energy-efficient,
	Summary \| Full Text:PDF(1.3MB)

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications Atsushi KOSHIBA Mikiko SATO Kimiyoshi USAMI Hideharu AMANO Ryuichi SAKAMOTO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 ; pp. 926-935 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: energy conservation, power gating, operating system, microprocessor,
	Summary \| Full Text:PDF(2.7MB)

RSFQ 4-bit Bit-Slice Integer Multiplier Guang-Ming TANG Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 ; pp. 697-702 Type of Manuscript: Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics) Category: Keyword: multiplier, single-flux-quantum (SFQ), microprocessor, superconducting integrated circuits,
	Summary \| Full Text:PDF(2MB)

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control Hideki ANDO Ryota SHIOYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/02/01 Vol. E99-D No. 2 ; pp. 341-350 Type of Manuscript: PAPER Category: Computer System Keyword: microprocessor, superscalar processor, memory-level parallelism, instruction-level parallelism, power consumption,
	Summary \| Full Text:PDF(638.6KB)

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 ; pp. 536-543 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: microprocessor, low power design,
	Summary \| Full Text:PDF(2.2MB)

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism Yuya KORA Kyohei YAMAGUCHI Hideki ANDO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/12/01 Vol. E97-D No. 12 ; pp. 3110-3123 Type of Manuscript: PAPER Category: Computer System Keyword: microprocessor, superscalar processor, memory-level parallelism, instruction-level parallelism,
	Summary \| Full Text:PDF(1.6MB)

Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification Kyohei YAMAGUCHI Yuya KORA Hideki ANDO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/09/01 Vol. E95-D No. 9 ; pp. 2235-2246 Type of Manuscript: PAPER Category: Computer System Keyword: microprocessor, superscalar processor, issue queue, delay, complexity,
	Summary \| Full Text:PDF(874.5KB)

A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors Makoto SUGIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 477-486 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: soft error, NBTI, SEU, SET, control signal error, continuous signature monitoring, reliability, vulnerability, microprocessor,
	Summary \| Full Text:PDF(485.3KB)

A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2533-2541 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: microprocessor, low-power design, embedded systems, real-time systems,
	Summary \| Full Text:PDF(741.9KB)

Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction Yusuke TANAKA Hideki ANDO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/12/01 Vol. E93-D No. 12 ; pp. 3294-3305 Type of Manuscript: PAPER Category: Computer System Keyword: microarchitecture, microprocessor, instruction pre-execution, value prediction, register file,
	Summary \| Full Text:PDF(541.3KB)

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation Kazunaga HYODO Kengo IWAMOTO Hideki ANDO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/11/01 Vol. E92-D No. 11 ; pp. 2186-2195 Type of Manuscript: PAPER Category: Computer Systems Keyword: microarchitecture, microprocessor, instruction pre-execution, low power,
	Summary \| Full Text:PDF(520.3KB)

Bit-Serial Single Flux Quantum Microprocessor CORE Akira FUJIMAKI Masamitsu TANAKA Takahiro YAMADA Yuki YAMANASHI Heejoung PARK Nobuyuki YOSHIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/03/01 Vol. E91-C No. 3 ; pp. 342-349 Type of Manuscript: INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics) Category: Keyword: superconductor, microprocessor, single flux quantum, bit-serial, LSI,
	Summary \| Full Text:PDF(929.4KB)

Design Development of SPARC64 V Microprocessor Mariko SAKAMOTO Akira KATSUNO Aiichiro INOUE Takeo ASAKAWA Kuniki MORITA Tsuyoshi MOTOKURUMADA Yasunori KIMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 ; pp. 1955-1965 Type of Manuscript: INVITED PAPER (Special Issue on Development of Advanced Computer Systems) Category: Keyword: microprocessor, microarchitecture, UNIX server, enterprise server, software performance simulator,
	Summary \| Full Text:PDF(5.2MB)

A 12.8 GOPS/2.1GFLOPS 8-Way VLIW Embedded Processor with Advanced Multimedia Mechanism Yasuki NAKAMURA Hiroshi OKANO Atsuhiro SUGA Hiromasa TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 ; pp. 529-534 Type of Manuscript: INVITED PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Keyword: VLIW, microprocessor, multimedia,
	Summary \| Full Text:PDF(1.1MB)

Design of Small RSFQ Microprocessor Based on Cell-Based Top-Down Design Methodology Futabako MATSUZAKI Kenichi YODA Junichi KOSHIYAMA Kei MOTOORI Nobuyuki YOSHIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/03/01 Vol. E85-C No. 3 ; pp. 659-664 Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics) Category: Digital Devices and Their Applications Keyword: SFQ, BDD, superconducting circuit, microprocessor, standard cell,
	Summary \| Full Text:PDF(711.2KB)

200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology Tatsuo TERUYAMA Tetsuo KAMADA Masashi SASAHARA Shardul KAZI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 ; pp. 235-242 Type of Manuscript: INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Keyword: microprocessor, MIPS, SIMD, tiling, network,
	Summary \| Full Text:PDF(864.2KB)

Trends in High-Performance, Low-Power Cache Memory Architectures Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 ; pp. 304-314 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: High-Performance Technologies Keyword: cache, low power, high performance, microprocessor, survey,
	Summary \| Full Text:PDF(238.5KB)

Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores Nozomu TOGAWA Yoshiharu KATAOKA Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2639-2647 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: area estimation, delay estimation, hardware/software cosynthesis, digital signal processor (DSP), microprocessor,
	Summary \| Full Text:PDF(412KB)

A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-Way VLIW Embedded Microprocessor Hiroshi OKANO Atsuhiro SUGA Hideo MIYAKE Yoshimasa TAKEBE Yasuki NAKAMURA Hiromasa TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 ; pp. 150-156 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: VLIW, microprocessor, multimedia, SIMD, synthesis,
	Summary \| Full Text:PDF(823.7KB)

Adaptive Image Enhancement Algorithms and Their Implementation for Real-Time Video Signals Ichiro KURODA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/02/01 Vol. E84-A No. 2 ; pp. 390-399 Type of Manuscript: TUTORIAL PAPER Category: Keyword: image enhancement, 2-D filtering, fast algorithm, parallel processing, microprocessor,
	Summary \| Full Text:PDF(1.3MB)

A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/01/25 Vol. E83-C No. 1 ; pp. 109-114 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: cache, SRAM, low power, two-port, microprocessor,
	Summary \| Full Text:PDF(1.4MB)

Low Voltage/Low Power CMOS VCO Changku HWANG Masaru KOKUBO Hirokazu AOKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/03/25 Vol. E82-A No. 3 ; pp. 424-430 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: microprocessor, PLL, V-I converter, current and voltage controlled oscillator (CCO and VCO),
	Summary \| Full Text:PDF(402.8KB)

A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor Akira YAMADA Toyohiko YOSHIDA Tetsuya MATSUMURA Shin-ichi URAMOTO Koji TSUCHIHASHI Edgar HOLMANN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 ; pp. 1382-1390 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: multimedia processor, media processor, VLIW, MPEG, microprocessor,
	Summary \| Full Text:PDF(1005.9KB)

A Dual-Issue RISC Processor for Multimedia Signal Processing Hisakazu SATO Toyohiko YOSHIDA Masahito MATSUO Toru KENGAKU Koji TSUCHIHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 ; pp. 1374-1381 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: multimedia, DSP, microprocessor, VLIW,
	Summary \| Full Text:PDF(739.3KB)

A 2 V 250 MHz VLIW Multimedia Processor Toyohiko YOSHIDA Akira YAMADA Edgar HOLMANN Hidehiro TAKATA Atsushi MOHRI Yukihiko SHIMAZU Kiyoshi NAKAKIMURA Keiichi HIGASHITANI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 ; pp. 651-660 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: multimedia processor, media processor, VLIW, MPEG, AC-3, microprocessor,
	Summary \| Full Text:PDF(1.1MB)

Analog Circuit Design Methodology in a Low Power RISC Microprocessor Koichiro ISHIBASHI Hisayuki HIGUCHI Toshinobu SHIMBO Kunio UCHIYAMA Kenji SHIOZAWA Naotaka HASHIMOTO Shuji IKEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/02/25 Vol. E81-A No. 2 ; pp. 210-217 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era) Category: Keyword: microprocessor, TLB, CAM, 0. 35 µm, CMOS,
	Summary \| Full Text:PDF(882.4KB)

Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 ; pp. 1539-1545 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: RISC, architecture, low power, high speed, microprocessor,
	Summary \| Full Text:PDF(674.5KB)

SEWD: A Cache Architecture to Speed up the Misaligned Instruction Prefetch Joon-Seo YIM In-Cheol PARK Chong-Min KYUNG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/07/25 Vol. E80-D No. 7 ; pp. 742-745 Type of Manuscript: LETTER Category: Computer Hardware and Design Keyword: cache, microprocessor, pipeline,
	Summary \| Full Text:PDF(303.7KB)

Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/03/25 Vol. E79-C No. 3 ; pp. 424-429 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: low power, partitioned-bus architecture, variable-width-bus scheme, microprocessor,
	Summary \| Full Text:PDF(513.1KB)

Data Bypassing Register File for Low Power Microprocessor Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/10/25 Vol. E78-C No. 10 ; pp. 1470-1472 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: low power, data bypassing register file, microprocessor, implicit data bypassing scheme,
	Summary \| Full Text:PDF(259.9KB)

A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor Hiroaki SUZUKI Toshichika SAKAI Hisao HARIGAI Yoichi YANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/25 Vol. E78-C No. 4 ; pp. 389-393 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Digital Circuits Keyword: RISC, microprocessor, CMOS LSI, low-power,
	Summary \| Full Text:PDF(451.6KB)

A 12-bit Resolution 200 kFLIPS Fuzzy Inference Processor Kazuo NAKAMURA Narumi SAKASHITA Yasuhiko NITTA Kenichi SHIMOMURA Takeshi TOKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 ; pp. 1102-1111 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Fuzzy Logic System Keyword: fuzzy inference, rule, membership function, microprocessor,
	Summary \| Full Text:PDF(835.7KB)

Design Considerations for Low-Voltage Crystal Oscillator Circuit in a 1.8-V Single Chip Microprocessor Shigeo KUBOKI Takehiro OHTA Junichi KONO Yoji NISHIO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/05/25 Vol. E76-C No. 5 ; pp. 701-707 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits) Category: Keyword: crystal oscillator, CMOS oscillation circuit, open loop-gain, microprocessor, low voltage oscillator,
	Summary \| Full Text:PDF(545.9KB)

High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor Shigeo KUNINOBU Tamotsu NISHIYAMA Takashi TANIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 ; pp. 436-445 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: multiplier, divider, redundant binary, microprocessor,
	Summary \| Full Text:PDF(852.9KB)

A Design of Static Operatable Low-Power 16-bit Microprocessor Hiroaki KANEKO Takashi MIYAZAKI Hideki SUGIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/10/25 Vol. E75-C No. 10 ; pp. 1188-1195 Type of Manuscript: Special Section PAPER (Special Issue on Microprocessors) Category: Low-Voltage Operation Keyword: ASSP, CMOS device, CPU core, microprocessor, power consumption, static operation,
	Summary \| Full Text:PDF(692.6KB)