Keyword : merged DRAM/logic LSIs


A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1716-1723
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
cachelow powervariable line-sizemerged DRAM/logic LSIshigh bandwidth
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Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5 ; pp. 1048-1057
Type of Manuscript:  PAPER
Category: Computer System Element
Keyword: 
cachevariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF

High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1438-1447
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
cachemerged DRAM/logic LSIsmemory system
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Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs
Koji KAI Akihiko INOUE Taku OHSAWA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1448-1454
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
merged DRAM/logic LSIsdata retention timerefreshyield
 Summary | Full Text:PDF