Keyword : memory


Nonvolatile Polymer Memory-Cell Embedded with Ni Nanocrystals Surrounded by NiO in Polystyrene
HyunMin SEUNG Jong-Dae LEE Chang-Hwan KIM Jea-Gun PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/05/01
Vol. E96-C  No. 5 ; pp. 699-701
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
nonvolatilepolymermemorynanocrystalNi
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High Throughput Turbo Decoding Scheme
Jaesung CHOI Joonyoung SHIN Jeong Woo LEE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/06/01
Vol. E95-B  No. 6 ; pp. 2109-2112
Type of Manuscript:  LETTER
Category: Fundamental Theories for Communications
Keyword: 
turbo decoderthroughputclock cyclememory
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Ant Colony Optimization with Memory and Its Application to Traveling Salesman Problem
Rong-Long WANG Li-Qing ZHAO Xiao-Fan ZHOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/03/01
Vol. E95-A  No. 3 ; pp. 639-645
Type of Manuscript:  PAPER
Category: Numerical Analysis and Optimization
Keyword: 
ant colony optimizationmemorycombinatorial optimization problemstraveling salesman problem
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A Single Element Phase Change Memory
Sang-Hyeon LEE Moonkyung KIM Byung-ki CHEONG Jooyeon KIM Jo-Won LEE Sandip TIWARI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5 ; pp. 676-680
Type of Manuscript:  INVITED PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
memoryphase change memoryPCMnonvolatileGST
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Dependence of Ag Film Thickness on Ag Nanocrystals Formation to Fabricate Polymer Nonvolatile Memory
Jong-Dae LEE Hyun-Min SEUNG Kyoung-Cheol KWON Jea-Gun PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5 ; pp. 850-853
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
polymernonvolatilememorynanocrystal
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The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction
Ki-Sang JUNG Kang-Jik KIM Young-Eun KIM Jin-Gyun CHUNG Ki-Hyun PYUN Jong-Yeol LEE Hang-Geun JEONG Seong-Ik CHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/03/01
Vol. E92-C  No. 3 ; pp. 352-355
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
ROMHG (Half Grouping)memory
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Quasi-Hierarchical Routing Algorithm for ZigBee/IEEE 802.15.4 Networks
Youn-Soo KIM Eun Ju LEE Bong Soo KIM Hyung Seok KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/08/01
Vol. E91-A  No. 8 ; pp. 2269-2271
Type of Manuscript:  LETTER
Category: Mobile Information Network and Personal Communications
Keyword: 
wireless sensor networkZigBeeroutingmemory
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Electrical Characterization of Nano-Floating Gated Silicon-on-Insulator Memory with In2O3 Nano-Particles Embedded in Polyimide Insulator
Dong Uk LEE Seon Pil KIM Tae Hee LEE Eun Kyu KIM Hyun-Mo KOO Won-Ju CHO Young-Ho KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5 ; pp. 747-750
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
In2O3memorySOInano-particlesnonvolatile
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Successive Writing/Rewriting on Composite Conducting Polymer
Masaharu FUJII Haruo IHORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/12/01
Vol. E89-C  No. 12 ; pp. 1732-1734
Type of Manuscript:  Special Section PAPER (Special Section on Towards the Realization of Organic Molecular Electronics)
Category: Fabrication of Organic Materials
Keyword: 
conducting polymerwritingmemorypolypyrrolepoly(3-hexylthiophene)
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A High Resolution, Wide Range Digital Impedance Controller
Tae-Hyoung KIM Kwang-Jin LEE Uk-Rae CHO Hyun-Geun BYUN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8 ; pp. 1723-1725
Type of Manuscript:  Special Section LETTER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
memoryimpedance controlinterface circuiteye window
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A 0.24 µm PRAM Cell Technology Using N-Doped GeSbTe Films
Hideki HORII Jeong Hee PARK Ji Hye YI Bong Jin KUH Yong Ho HA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/10/01
Vol. E87-C  No. 10 ; pp. 1673-1678
Type of Manuscript:  Special Section PAPER (Special Section on New Era of Nonvolatile Memories)
Category: Phase Change RAM
Keyword: 
PRAMphase changeGeSbTeCMOSmemoryN-dopedchalcogenide
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A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure
Yeonbae CHUNG Jung-Hyun KIM Jae-Eun YOON 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/10/01
Vol. E87-C  No. 10 ; pp. 1686-1693
Type of Manuscript:  Special Section PAPER (Special Section on New Era of Nonvolatile Memories)
Category: Ferroelectric Memory
Keyword: 
FeRAMmemorynonvolatileferroelectrics
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Perspectives of Low-Power VLSI's
Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 429-436
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
digitalmemoryapplicationlow powerVLSIleakage
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High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology
Akira FUJIMAKI Yoshiaki TAKAI Nobuyuki YOSHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Vol. E85-C  No. 3 ; pp. 612-616
Type of Manuscript:  INVITED PAPER (Special Issue on Superconductive Electronics)
Category: Digital Devices and Their Applications
Keyword: 
SFQmemoryprocessorsuperconducting circuitJAVA
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A System Level Optimization Technique for Application Specific Low Power Memories
Tohru ISHIHARA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2755-2761
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
low power designhardware/software codesignmemorylow voltageembedded system
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A Model for High Frequency C-V Characteristics of Ferroelectric Capacitors
Nobuhito OGATA Hiroshi ISHIWARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6 ; pp. 777-784
Type of Manuscript:  Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
ferroelectricmemorytransistormodelsimulationC-V characteristic
 Summary | Full Text:PDF

Estimation of Imprint Failure Lifetime in FeRAM with Pt/SrBi2Ta2O9/Pt Capacitor
Young Min KANG Seaung Suk LEE Beelyong YANG Choong Heui CHUNG Hun Woo KYE Suk Kyoung HONG Nam Soo KANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6 ; pp. 757-762
Type of Manuscript:  Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
ferroelectricnonvolatilememoryFeRAMimprintreliability
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Overview and Trend of Chain FeRAM Architecture
Daisaburo TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6 ; pp. 747-756
Type of Manuscript:  INVITED PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
ferroelectricnonvolatilememoryFeRAMchain FeRAM
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Superconducting Technology for Digital Applications Using Niobium Josephson Junctions
Shuichi TAHARA Hideaki NUMATA Shinichi YOROZU Yoshihito HASHIMOTO Shuichi NAGASAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/01/25
Vol. E83-C  No. 1 ; pp. 60-68
Type of Manuscript:  INVITED PAPER (Special Issue on Superconductive Devices and Systems)
Category: Digital Applications
Keyword: 
Josephson junctionsplanarizationmoat structurememorynetwork
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A Memory Power Optimization Technique for Application Specific Embedded Systems
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2366-2374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
low power designhardware/software codesignmemoryembedded system
 Summary | Full Text:PDF

Chaotic Oscillations in SQUIDs for Logic Circuits
Mititada MORISUE Masahiro SAKAMOTO Tatsuwo NISHINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/07/25
Vol. E82-A  No. 7 ; pp. 1329-1335
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
SQUIDchaosmemoryfull adder
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Soft-Core Processor Architecture for Embedded System Design
Eko Fajar NURPRASETYO Akihiko INOUE Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1416-1423
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
scalable processordatapath widthmemory
 Summary | Full Text:PDF

Numerical Analysis of Metal-Ferroelectric-Semiconductor Field-Effect-Transistors (MFS-FETs) Considering Inhomogeneous Ferroelectric Polarization
Tatsuya KAMEI Eisuke TOKUMITSU Hiroshi ISHIWARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/04/25
Vol. E81-C  No. 4 ; pp. 577-583
Type of Manuscript:  Special Section PAPER (Special Issue on Advanced Memory Devices Using High-Dielectric-Constant and Ferroelectric Thin Films)
Category: 
Keyword: 
ferroelectricMFSFETSrBi2Ta2O9Si non-volatile memorymemory
 Summary | Full Text:PDF

Quantum-Dot Based Opto-Electronic Device
Kazumasa NOMOTO Ryuichi UGAJIN Toshi-kazu SUZUKI Kenichi TAIRA Ichiro HASE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/01/25
Vol. E81-C  No. 1 ; pp. 8-15
Type of Manuscript:  Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices)
Category: 
Keyword: 
quantum dotlight input/outputmemoryAND/OR deviceelectron relaxation
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Embedded System Cost Optimization via Data Path Width Adjustment
Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10 ; pp. 974-981
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High Level Synthesis
Keyword: 
embedded systemssystem on chipCPUmemory
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On Information Dumping Phenomenon in Free Recall Effects of Priority Instructions on Free Recall of Pictures and Words
Atsuo MURATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9 ; pp. 1729-1731
Type of Manuscript:  LETTER
Category: Human Communications and Ergonomics
Keyword: 
free recallmemorypriorityinformation dumping
 Summary | Full Text:PDF

A Long Data Retention SOI DRAM with the Body Refresh Function
Shigeki TOMISHIMA Fukashi MORISHITA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 899-904
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Structure Devices
Keyword: 
memorySOI-DRAMbody regionrefreshdata retention
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Planning and Design Issues for Information Delivery Using Idle Periods in Telecommunication Networks
Kenichi MASE Suwan RUNGGERATIGUL 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/02/25
Vol. E80-B  No. 2 ; pp. 230-239
Type of Manuscript:  INVITED PAPER (Special Issue on Telecommunications Network Planning and Design)
Category: 
Keyword: 
traffic variationmemorytelecommunication networkstrunk reservationnon-realtime servicedimensioningminimum costpricing
 Summary | Full Text:PDF

The Possibility of Higher Temperature Operation in Quantum Cellular Automata (QCA)
Tetsufumi TANAMOTO Riichi KATOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/11/25
Vol. E79-C  No. 11 ; pp. 1550-1556
Type of Manuscript:  Special Section PAPER (Special Issue on Quantum Effect Devices and Their Fabrication Technologies)
Category: 
Keyword: 
quantum cellular automata (QCA)hubbard modelquantum dotmemorylayered structure
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Josephson Memory Technology
Suichi TAHARA Shuichi NAGASAWA Hideaki NUMATA Yoshihito HASHIMOTO Shinichi YOROZU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/09/25
Vol. E79-C  No. 9 ; pp. 1193-1199
Type of Manuscript:  INVITED PAPER (Special Issue on Toward Digital and Analog Applications of Superconductors)
Category: Superconductive digital integrated circuits
Keyword: 
Josephsonmemoryflux trapbuilt-in self testing
 Summary | Full Text:PDF

111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method
Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 735-742
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
memorysynchronous SRAMhigh speed SRAM, low powerclock
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Ferroelectric Nonvolatile Memory Technology
Tatsumi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 812-818
Type of Manuscript:  INVITED PAPER (Special Issue on ULSI Memory Technology)
Category: Nonvolatile memories
Keyword: 
ferroelectricnonvolatilememorymaterialcellarchitecture,Y1,256 kbit FeRAM
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A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs
Shigeki TOMISHIMA Shigehiro KUGE Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 808-811
Type of Manuscript:  Special Section LETTER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memorytriple metalsource linelayout
 Summary | Full Text:PDF

NAND-Structured DRAM Cell with Lithography-Oriented Design
Masami AOKI Tohru OZAKI Takashi YAMADA Takeshi HAMAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 792-797
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memoryDRAMstacked capacitor
 Summary | Full Text:PDF

A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
Isao NARITAKE Tadahiko SUGIBAYASHI Satoshi UTSUGI Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 787-791
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memoryDRAMhierarchical bit-linerefresh
 Summary | Full Text:PDF

Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology
Takakuni DOUSEKI Shin'ichiro MUTOH Takemi UEKI Junzo YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2 ; pp. 179-184
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Device and Circuit Characterization
Keyword: 
soft-error1-voltmulti-thresholdCMOSmemory
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NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond
Takeshi HAMAMOTO Yutaka ISHIBASHI Masami AOKI Yoshihiko SAITOH Takashi YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 789-796
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
memoryDRAMtrenchcapacitor
 Summary | Full Text:PDF

BIST Circuit Macro Using Microprogram ROM for LSI Memories
Hiroki KOIKE Toshio TAKESHIMA Masahide TAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 838-844
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
memoryBISTROMtestermacro
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ULSI Memory for Multimedia Applications
Yasuo AKATSUKA Yoichi YANO Shigeo NIITSU Akihiko MORINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 766-772
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
ULSImemorymultimediaapplication
 Summary | Full Text:PDF

A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age
Yuji SAKAI Kanji OISHI Miki MATSUMOTO Shoji WADA Tadamichi SAKASHITA Masahiro KATAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 782-788
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
DRAMsynchronous operationmemory
 Summary | Full Text:PDF

A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
Nobutaro SHIBATA Mayumi WATANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 797-804
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
marcocellmemorysynchronouslow powerlatch type
 Summary | Full Text:PDF

A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs
Tadahiko SUGIBAYASHI Isao NARITAKE Hiroshi TAKADA Ken INOUE Ichiro YAMAMOTO Tatsuya MATANO Mamoru FUJITA Yoshiharu AIMOTO Toshio TAKESHIMA Satoshi UTSUGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1323-1327
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
memoryDRAMtest
 Summary | Full Text:PDF

The Trend of Functional Memory Development
Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1545-1554
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
memoryfunctional memorycontent addressable memoryassociative memoryprocessor array
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High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1641-1648
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
ASICCMOSmacrocellmemoryconfigurablerow sliceabledecodershort design Turn-Around-Time (TAT)
 Summary | Full Text:PDF

Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement
Ken-ichi IMAMIYA Jun-ichi MIYAMOTO Nobuaki OHTSUKA Naoto TOMITA Yumiko IYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1626-1631
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Non-volatile Memory
Keyword: 
redundancymemoryyieldEPROM
 Summary | Full Text:PDF

Stabilization of Voltage Limiter Circuit for High-Density DRAM's Using Pole-Zero Compensation
Hitoshi TANAKA Masakazu AOKI Jun ETOH Masashi HORIGUCHI Kiyoo ITOH Kazuhiko KAJIGAYA Tetsurou MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11 ; pp. 1333-1343
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
memoryDRAMvoltage limiterpole-zero compensation
 Summary | Full Text:PDF