Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA Makoto SAENTadanobu TOBAYusuke KANNO
Publication: Publication Date: 2017/04/01 Vol. E100-CNo. 4 ;
pp. 382-390 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: FPGA, soft-error tolerance, memory controller, configuration RAM,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-ANo. 12 ;
pp. 2810-2817 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: FPGA-based hardware emulators, SDRAM, memory controller, clock generator,
