Keyword : memory cell

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
Hirofumi SHINOHARA Koji NII Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1488-1500
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
SRAM, memory cell, static noise margin, SNM, variability, 
 Summary | Full Text:PDF
Low-Power Switched Current Memory Cell with CMOS-Type Configuration
Masashi KATO Nobuyuki TERADA Hirofumi OHATA Eisuke ARAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/01/01
Vol. E91-C  No. 1 ; pp. 120-121
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
switched current, low-power, CMOS-type, memory cell, 
 Summary | Full Text:PDF
A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12 ; pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAM, power dissipation, reliability, bit-line, wordline, small swing, threshold voltage, sense amplifier, memory cell, 
 Summary | Full Text:PDF
A Capacitor over Bit-Line (COB) Stacked Capacitor Cell Using Local Interconnect Layer for 64 MbDRAMs
Naoki KASAI Masato SAKAO Toshiyuki ISHIJIMA Eiji IKAWA Hirohito WATANABE Toshio TAKESHIMA Nobuhiro TANABE Kazuo TERADA Takamaro KIKKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4 ; pp. 548-555
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAM, memory cell, stacked capacitor, local interconnect, 
 Summary | Full Text:PDF