Keyword : master and slave scan paths

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3 ; pp. 433-442
Type of Manuscript:  PAPER
Category: Dependable Computing
dual circuitsmaster and slave scan pathsdelay fault testingconcurrent error detectionDFT
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