IEICE Trans

Keyword : macrocell

A Novel Radio Resource Optimization Scheme in Closed Access Femtocell Networks Based on Bat Algorithm I Wayan MUSTIKA Nifty FATH Selo SULISTYO Koji YAMAMOTO Hidekazu MURATA
Publication: Publication Date: 2019/04/01 Vol. E102-B No. 4 ; pp. 660-669 Type of Manuscript: INVITED PAPER (Special Section on Sensing, Wireless Networking, Data Collection, Analysis and Processing Technologies for Ambient Intelligence with Internet of Things) Category: Keyword: heterogeneous network, macrocell, femtocell, resource allocation, optimization, bat algorithm, interference management,
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A Stackelberg Game Based Pricing and User Association for Spectrum Splitting Macro-Femto HetNets Bo GU Zhi LIU Cheng ZHANG Kyoko YAMORI Osamu MIZUNO Yoshiaki TANAKA
Publication: Publication Date: 2018/01/01 Vol. E101-B No. 1 ; pp. 154-162 Type of Manuscript: PAPER Category: Network Keyword: HetNet, macrocell, femtocell, user association, utility, pricing, revenue optimization, game,
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Interference Mitigation Framework Based on Interference Alignment for Femtocell-Macrocell Two Tier Cellular Systems Mohamed RIHAN Maha ELSABROUTY Osamu MUTA Hiroshi FURUKAWA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2015/03/01 Vol. E98-B No. 3 ; pp. 467-476 Type of Manuscript: PAPER Category: Wireless Communication Technologies Keyword: Interference Alignment (IA), femtocell, macrocell, Cognitive Radio (CR), Restricted Water-Filling (RWF) algorithm, Iterative Reweighted Least Squares (IRLS), Multi-Input Multi-Output (MIMO),
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Fair Partitioning of the Downlink Resources of an OFDMA-Based Multi-User Multi-Tier Cellular Network Using Fractional Frequency Reuse Akindele Segun AFOLABI Erdenebileg MUNKHBAT Yumi TAKAKI Chikara OHTA Hisashi TAMAKI Yoshizo TANAKA Takashi YAMAMOTO Yoji OKADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2012/10/01 Vol. E95-B No. 10 ; pp. 3353-3357 Type of Manuscript: LETTER Category: Wireless Communication Technologies Keyword: resource partitioning, OFDMA, FFR, macrocell, femtocell,
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Teletraffic Performance of a Hierarchical Microcell/Macrocell PCS Architecture Jaeshin JANG Byung-Cheol SHIN Seung Hwa YOO Byung Chul KIM Chong Ho YOON
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2001/05/01 Vol. E84-B No. 5 ; pp. 1362-1374 Type of Manuscript: PAPER Category: Wireless Communication Switching Keyword: handoff, microcell, macrocell, PBS, FCFS,
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An Efficient Channel Allocation Scheme for Multicast Traffic in Multitier Cellular Systems Il HAN Dong-Ho CHO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2001/04/01 Vol. E84-B No. 4 ; pp. 1087-1093 Type of Manuscript: LETTER Category: Wireless Communication Technology Keyword: multicast, multitier, channel allocation, microcell, macrocell,
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Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/25 Vol. E82-C No. 1 ; pp. 94-104 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, macrocell, size-configurable, high speed, low power, per-bitline architecture, current-sense amplifier, squashed memory cell, trench isolation,
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Guided-Probe Diagnosis of LSIs Containing Macrocells Norio KUJI Tadao TAKEDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 ; pp. 731-737 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Beam Testing/Diagnosis Keyword: electron beam tester, guided-probe diagnosis, macrocell, memory macro, logic simulation, logic model, CAD navigation,
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A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 ; pp. 1598-1607 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, low power, virtual GND, column address, synchronous, macrocell,
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High-Performance Memory Macrocells with Row and Column Sliceable Architecture Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 ; pp. 1641-1648 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: ASIC, CMOS, macrocell, memory, configurable, row sliceable, decoder, short design Turn-Around-Time (TAT),
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