Keyword : low-power SRAM

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
Hiroki NOGUCHI Yusuke IGUCHI Hidehiro FUJIWARA Shunsuke OKUMURA Yasuhiro MORITA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 543-552
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
8T SRAM cell, 10T SRAM cell, low-power SRAM, non-precharge SRAM, two-port SRAM, video processing, 
 Summary | Full Text:PDF
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's
Kyeong-Sik MIN Kouichi KANDA Hiroshi KAWAGUCHI Kenichi INAGAKI Fayez Robert SALIBA Hoon-Dae CHOI Hyun-Young CHOI Daejeong KIM Dong Myong KIM Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 760-767
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
low-voltage SRAM, low-power SRAM, row-by-row, low-leakage, leakage reduction technique, leakage suppression technique, subthreshold current, 
 Summary | Full Text:PDF