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| Keyword : low power
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An Integrated Wideband Operational Transconductance Amplifier with Complementary Slew-Rate Enhancer
Deng-Fong LU Chin HSIA Kun-Chu LEE | Publication:
Publication Date: 2020/01/01
Vol. E103-A
No. 1 ;
pp. 295-296
Type of Manuscript:
Special Section LETTER (Special Section on Wideband Systems)
Category:
Keyword:
wideband OTA, low power, slew-rate, | | | Summary | Full Text:PDF | |
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A Low Power Pulse Generator for Test Platform Applications
Jen-Chieh LIU Pei-Ying LEE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A
No. 7 ;
pp. 1415-1416
Type of Manuscript:
Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category:
Keyword:
arbitrary waveform, pulse generator, low power, | | | Summary | Full Text:PDF | |
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A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/05/01
Vol. E98-A
No. 5 ;
pp. 1058-1066
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
Reed-Solomon code, syndrome key equation solution, low power, folding, | | | Summary | Full Text:PDF | |
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Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC
Jeong-Gun LEE Myeong-Hoon OH | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C
No. 4 ;
pp. 253-263
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
asynchronous circuit, FPGA device, MIPS processor, low power, | | | Summary | Full Text:PDF | |
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Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters
Takashi MIYAMORI Hui XU Hiroyuki USUI Soichiro HOSODA Toru SANO Kazumasa YAMAMOTO Takeshi KODAKA Nobuhiro NONOGAKI Nau OZAKI Jun TANABE | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C
No. 4 ;
pp. 360-368
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
many-core, network-on-chip, VLIW, low power, face detection, H.264, super resolution, | | | Summary | Full Text:PDF | |
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A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC
Muchen LI Jinjia ZHOU Dajiang ZHOU Xiao PENG Satoshi GOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A
No. 6 ;
pp. 1366-1375
Type of Manuscript:
Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category:
Keyword:
HEVC, H.264/AVC, deblocking filter, dual-mode, low power, SHV, HD, | | | Summary | Full Text:PDF | |
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Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors
Kazuhito ITO Takuya NUMATA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C
No. 4 ;
pp. 463-472
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
low power, functional unit, narrow operand, | | | Summary | Full Text:PDF | |
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Region Oriented Routing FPGA Architecture for Dynamic Power Gating
Ce LI Yiping DONG Takahiro WATANABE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12 ;
pp. 2199-2207
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
FPGA, low power, switch box, routing, | | | Summary | Full Text:PDF | |
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A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/04/01
Vol. E95-A
No. 4 ;
pp. 767-775
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
Viterbi decoder, convolutional code, trace back, survivor memory, low power, | | | Summary | Full Text:PDF | |
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Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12 ;
pp. 2519-2527
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
FPGA, low power, power domain, power consumption, | | | Summary | Full Text:PDF | |
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A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling
Byung-Do YANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12 ;
pp. 2676-2684
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword:
charge-recycling, DC-DC conversion, low power, on-chip, | | | Summary | Full Text:PDF | |
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An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder
Sung-Jin KIM Minchang CHO SeongHwan CHO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C
No. 6 ;
pp. 785-795
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
EPCglobal, Class 1, Generation 2, RFID, RFID tag, pulse interval encoded, passive, low power, PIE decoder, calibration, | | | Summary | Full Text:PDF | |
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Low-Power Embedded Processor Design Using Branch Direction
Gi-Ho PARK Jung-Wook PARK Gunok JUNG Shin-Dug KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12 ;
pp. 3180-3181
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
low power, BTB, wordline gating, | | | Summary | Full Text:PDF | |
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A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter
Shunsuke OKURA Tetsuro OKURA Toru IDO Kenji TANIGUCHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A
No. 2 ;
pp. 367-373
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
CMOS, pipelined ADC, settling, boost, low power, | | | Summary | Full Text:PDF | |
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55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
Tomohiko ITO Daisuke KUROSE Takeshi UENO Takafumi YAMAJI Tetsuro ITAKURA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C
No. 6 ;
pp. 887-893
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
A/D, ADC, pipeline, low power, amplifier, pseudo-differential amplifier, I/Q sharing, | | | Summary | Full Text:PDF | |
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Extended MPEG Video Format for Efficient Dynamic Voltage Scaling
Kwanhu BANG Sung-Yong BANG Eui-Young CHUNG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/05/01
Vol. E91-A
No. 5 ;
pp. 1283-1287
Type of Manuscript:
LETTER
Category: VLSI Design Technology and CAD
Keyword:
low power, energy, DVS, video, decoding, MPEG, | | | Summary | Full Text:PDF | |
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A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's
Fayez Robert SALIBA Hiroshi KAWAGUCHI Takayasu SAKURAI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C
No. 4 ;
pp. 743-748
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword:
active leakage, low power, SRAM, | | | Summary | Full Text:PDF | |
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Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications
Satoshi KOMATSU Masahiro FUJITA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A
No. 12 ;
pp. 3282-3289
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword:
bus encoding, ECC/EDC, low power, reliability, | | | Summary | Full Text:PDF | |
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Quality and Power Efficient Architecture for the Discrete Cosine Transform
Chi-Chia SUNG Shanq-Jang RUAN Bo-Yao LIN Mon-Chau SHIE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A
No. 12 ;
pp. 3500-3507
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword:
Loeffler DCT, binDCT, DAA, SSIM, low power, | | | Summary | Full Text:PDF | |
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Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy
Hidekazu TANAKA Koji INOUE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A
No. 12 ;
pp. 3274-3281
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword:
low power, cache, way prediction, confidence information, | | | Summary | Full Text:PDF | |
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Frequency-Scaling Approach for Managing Power Consumption in NOCs
Chun-Lung HSU Wen-Tso WANG Ying-Fu HONG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A
No. 12 ;
pp. 3580-3583
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
frequency-scaling, low power, NOC, FPGA, | | | Summary | Full Text:PDF | |
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A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic
Jianping HU Tiefeng XU Hong LI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D
No. 7 ;
pp. 1479-1485
Type of Manuscript:
Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword:
register file, low power, adiabatic logic, VLSI design, | | | Summary | Full Text:PDF | |
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Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A
No. 4 ;
pp. 862-868
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
low power, cache, leakage, | | | Summary | Full Text:PDF | |
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Low Area and Low Power Structures of DCT-Based Noise Generation System
Dae-Ik KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A
No. 9 ;
pp. 2466-2470
Type of Manuscript:
LETTER
Category: VLSI Design Technology and CAD
Keyword:
low area, low power, DCT, central limit theorem, | | | Summary | Full Text:PDF | |
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A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor
Toshihiro HATTORI Kenji OGURA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4 ;
pp. 520-526
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
threshold voltage, low power, dual-Vth, physical synthesis, | | | Summary | Full Text:PDF | |
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Low Voltage and Low Power CMOS Exponential-Control Variable-Gain Amplifier
Weihsing LIU Shen-Iuan LIU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Vol. E87-A
No. 4 ;
pp. 952-954
Type of Manuscript:
LETTER
Category: Circuit Theory
Keyword:
CMOS, low voltage, low power, exponential-control, VGA, | | | Summary | Full Text:PDF | |
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Perspectives of Low-Power VLSI's
Takayasu SAKURAI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4 ;
pp. 429-436
Type of Manuscript:
INVITED PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
digital, memory, application, low power, VLSI, leakage, | | | Summary | Full Text:PDF | |
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Power Analysis and Estimation for SOC Design: Techniques and Tools
Yun CAO Hiroto YASUURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/02/01
Vol. E87-A
No. 2 ;
pp. 410-416
Type of Manuscript:
REVIEW PAPER
Category: VLSI Design Technology and CAD
Keyword:
low power, SOC, power analysis, power estimation, | | | Summary | Full Text:PDF | |
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Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A
No. 4 ;
pp. 799-805
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
low power, instruction ROM, embedded systems, encoding, | | | Summary | Full Text:PDF | |
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Low Power Motion Estimation and Motion Compensation Block IPs in MPEG-4 Video Codec Hardware for Portable Applications
Chi-Weon YOON Hoi-Jun YOO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C
No. 4 ;
pp. 553-560
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword:
low power, motion estimation, motion compensation, MPEG-4, | | | Summary | Full Text:PDF | |
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Adaptive Bitwidth Compression for Low Power Video Memory Design
Vasily MOSHNYAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A
No. 4 ;
pp. 797-803
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
bit-compression, low power, video memory, adaptive technique, | | | Summary | Full Text:PDF | |
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SIMD ISA Extensions: Power Efficiency on Multimedia on a Superscalar Processor
Julien SEBOT Nathalie DRACH | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2 ;
pp. 297-303
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword:
multimedia, SIMD, superscalar, low power, | | | Summary | Full Text:PDF | |
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Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2 ;
pp. 279-287
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword:
cache, low power, look up, run time, | | | Summary | Full Text:PDF | |
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Issue Queue Energy Reduction through Dynamic Voltage Scaling
Vasily G. MOSHNYAGA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2 ;
pp. 272-278
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword:
issue queue, computer architecture, low power, voltage scaling, | | | Summary | Full Text:PDF | |
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Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A
No. 1 ;
pp. 234-240
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
low power, glitch, gate sizing, buffer insertion, | | | Summary | Full Text:PDF | |
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Motion Estimation with Power Scalability and Its VHDL Model
Ayuko TAKAGI Shogo MURAMATSU Hitoshi KIYA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A
No. 8 ;
pp. 1608-1613
Type of Manuscript:
Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword:
low power, motion estimation, MPEG, less gray level image, | | | Summary | Full Text:PDF | |
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A Flip-Flop Circuit with a Directly Controlled Emitter-Follower and a Level Stabilizer for Low-Power Prescalers
Hisayasu SATO Nagisa SASAKI Takahiro MIKI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C
No. 3 ;
pp. 504-510
Type of Manuscript:
Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword:
prescaler, flip-flop, emitter-follower, low power, | | | Summary | Full Text:PDF | |
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High Frequency Characteristics of Dynamic Threshold-Voltage MOSFET (DTMOS) under Ultra-Low Supply Voltage
Tetsu TANAKA Youichi MOMIYAMA Toshihiro SUGII | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C
No. 3 ;
pp. 538-543
Type of Manuscript:
Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword:
SOI, DTMOS, Ft, Fmax, low power, | | | Summary | Full Text:PDF | |
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Three Dimensional Image Analysis of Multi-Field Driving Method for Reducing Multi-Media LCD Power Consumption
Haruhiko OKUMURA Goh ITOH | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1998/11/25
Vol. E81-C
No. 11 ;
pp. 1691-1696
Type of Manuscript:
Special Section PAPER (Special Issue on Electronic Displays)
Category:
Keyword:
driving method, multi-media, low power, TFT-LCD, | | | Summary | Full Text:PDF | |
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Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIs An Overview
Haruhiko ICHINO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C
No. 12 ;
pp. 1511-1522
Type of Manuscript:
INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category:
Keyword:
Si bipolar, high speed, low power, optical transmission, | | | Summary | Full Text:PDF | |
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The Potential of Ultrathin-Film SOI Devices for Low-Power and High-Speed Applications
Yuichi KADO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C
No. 3 ;
pp. 443-454
Type of Manuscript:
INVITED PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: Circuit Technologies and Applications
Keyword:
CMOS, SOI, SIMOX, low voltage, low power, | | | Summary | Full Text:PDF | |
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A Circuit Library for Low Power and High Speed Digital Signal Processor
Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C
No. 12 ;
pp. 1717-1725
Type of Manuscript:
Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category:
Keyword:
low power, high speed, low cost, GSM, PDC, NADC, digital signal processing, personal communication, 50 MIPS, CPU, | | | Summary | Full Text:PDF | |
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A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
Nobutaro SHIBATA Mayumi WATANABE | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C
No. 7 ;
pp. 797-804
Type of Manuscript:
Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category:
Keyword:
marcocell, memory, synchronous, low power, latch type, | | | Summary | Full Text:PDF | |
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An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors
Masakazu YAMASHINA Hachiro YAMADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C
No. 10 ;
pp. 1181-1187
Type of Manuscript:
Special Section PAPER (Special Issue on Microprocessors)
Category: Low-Voltage Operation
Keyword:
current mode logic, low power, high speed, MOS, | | | Summary | Full Text:PDF | |
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4) Physical-Layer Architecture Using Low-Power Technology
54-bit multiplier