Keyword : low jitter


A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
Chia-Wen CHANG Kai-Yu LO Hossameldin A. IBRAHIM Ming-Chiuan SU Yuan-Hua CHU Shyh-Jye JOU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/04/01
Vol. E99-C  No. 4 ; pp. 481-490
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
all-digital phase-locked loopdigitally controlled oscillatorlow voltagespur suppressionlow jitterlow spur
 Summary | Full Text:PDF(2.2MB)

A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications
Chia-Wen CHANG Yuan-Hua CHU Shyh-Jye JOU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/08/01
Vol. E98-C  No. 8 ; pp. 882-891
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
all-digital phase-locked loophierarchical digitally controlled oscillatorslow voltagelow powerfast lock-inlow jitter
 Summary | Full Text:PDF(3.6MB)

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
Kuo-Hsing CHENG Yu-Chang TSAI Chien-Nan Jimmy LIU Kai-Wei HONG Chin-Cheng KUO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/07/01
Vol. E92-C  No. 7 ; pp. 964-972
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
phase-locked loop (PLL)self-calibrationlow jittermulti-phase VCO
 Summary | Full Text:PDF(1.4MB)

Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--
Keiji KISHINE Noboru ISHIHARA Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/04/01
Vol. E84-C  No. 4 ; pp. 460-469
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock and data recoveryPLLduplicated looplow jitter2.5-Gb/s
 Summary | Full Text:PDF(1MB)

A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO
Masayuki MIZUNO Koichiro FURUTA Takeshi ANDOH Akira TANABE Takao TAMURA Hidenobu MIYAMOTO Akio FURUKAWA Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1560-1571
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
phase-locked looplow voltagelow jitterfast-lock time
 Summary | Full Text:PDF(974.5KB)