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| Keyword : logic
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Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ
Masaru SANADA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D
No. 3 ;
pp. 557-563
Type of Manuscript:
Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Fault Detection
Keyword:
IDDQ, bridging fault, logic, layout structure, fault diagnosis, | | | Summary | Full Text:PDF | |
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A 10-b 300-MHz Interpolated-Parallel A/D Converter
Hiroshi KIMURA Akira MATSUZAWA Takashi NAKAMURA Shigeki SAWADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C
No. 5 ;
pp. 778-786
Type of Manuscript:
Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category:
Keyword:
A/D converter, parallel, interpolation, high speed, high resolution, linearity, circuit, bipolar, submicrometer, folding, encoder, logic, | | | Summary | Full Text:PDF | |
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