Keyword : logic verification


Pattern Generation for Locating Logic Design Errors
Masahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/05/25
Vol. E77-A  No. 5 ; pp. 881-893
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary decision diagrampattern generationlogic diagnosisrectificationlogic verification
 Summary | Full Text:PDF(969.2KB)

Extraction of Behavioral Descriptions from Synchronous Sequential Circuits
Masahiko OHMURA Hiroto YASUURA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1239-1246
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
behavioral extractionlogic verification
 Summary | Full Text:PDF(580KB)

Parallel Binary Decision Diagram Manipulation
Shinji KIMURA Tsutomu IGAKI Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1255-1262
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagramparallel algorithmlogic verification
 Summary | Full Text:PDF(678.3KB)

A Logic Diagnosis Technique for Multiple Output Circuit
Naoaki SUGANUMA Nobuto UEDA Masahiro TOMITA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1263-1271
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic diagnosislogic error locationlogic verificationEXM-algorithm
 Summary | Full Text:PDF(737.1KB)