Keyword : logic transformation

Accelerating Logic Rewiring Using Implication Analysis Tree
Chin-Ngai SZE Wangning LONG Yu-Liang WU Jinian BIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2725-2736
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
alternative wirelogic transformationlogic synthesis
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