IEICE Trans

Keyword : logic synthesis

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow Daisuke SUZUKI Takahiro HANYU
Publication: Publication Date: 2021/08/01 Vol. E104-D No. 8 ; pp. 1111-1120 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: FPGA, nonvolatile logic, logic synthesis, hardware description language, standard-cell-based design,
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Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1374-1380 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: logic synthesis, technology mapping, FPGA, SAT,
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Synthesis Algorithm for Parallel Index Generator Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2451-2458 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: logic synthesis, index generation function,
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Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm Ming-Chih CHEN Shen-Fu HSIAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3221-3228 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: AES, VLSI, common subexpression elimination (CSE), information security, logic synthesis,
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Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 ; pp. 257-266 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic synthesis, dual-rail, RSFQ, binary decision diagrams (BDDs),
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Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries Debatosh DEBNATH Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 ; pp. 3443-3450 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, Boolean matching, cell-library binding, technology mapping, canonical form,
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Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition Masao MORIMOTO Yoshinori TANAKA Makoto NAGATA Kazuo TAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 ; pp. 3324-3331 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, ASDDL, asymmetric slope, differential logic, high speed,
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An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD Tomonori IZUMI Shin'ichi KOUYAMA Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 ; pp. 907-914 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: reconfigurable system, design technology, logic synthesis, variable ordering, look-up table,
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Timing Optimization Methodology Based on Replacing Flip-Flops by Latches Ko YOSHIKAWA Keisuke KANAMARU Yasuhiko HAGIHARA Shigeto INUI Yuichi NAKAMURA Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3151-3158 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, sequential circuit, timing optimization, level-sensitive latch, formal verification,
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Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser Naohiko SHIMIZU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3225-3229 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Design Methodology Keyword: logic synthesis, HDL conversion, SFL, verilog,
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Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design Nattha SRETASEREEKUL Hiroshi SAITO Euiseok KIM Metehan OZCAN Masashi IMAI Hiroshi NAKAMURA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3028-3037 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: asynchronous controllers, logic synthesis, Control Data Flow Graphs (CDFGs), Signal Transition Graphs (STGs),
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An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2715-2724 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: functional decomposition, BDDs, logic synthesis, FPGA,
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Accelerating Logic Rewiring Using Implication Analysis Tree Chin-Ngai SZE Wangning LONG Yu-Liang WU Jinian BIAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2725-2736 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: alternative wire, logic transformation, logic synthesis,
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Modular Synthesis of Timed Circuits Using Partial Order Reduction Tomohiro YONEDA Eric MERCER Chris MYERS
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2684-2692 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, partial order reduction, timed circuits, modular synthesis,
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Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications Shih-Chieh CHANG Zhong-Zhen WU Sheng-Hong TU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/12/01 Vol. E84-A No. 12 ; pp. 3116-3124 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic synthesis, redundant wire, alternative wire, mandatory assignment, layout synthesis,
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Generalized Reasoning Scheme for Redundancy Addition and Removal Jose Alberto ESPEJO Luis ENTRENA Enrique San MILLAN Celia LOPEZ
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2665-2672 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: redundancy addition and removal, rewiring, logic synthesis, structural methods,
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LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression Hiroshi TSUTSUI Akihiko TOMITA Shigenori SUGIMOTO Kazuhisa SAKAI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2681-2689 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: FPGA Systhesis Keyword: reconfigurable logic, programmable logic, system architecture and design, logic synthesis, sum of products,
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Timing Driven Gate Duplication in Technology Independent Phase Ankur SRIVASTAVA Chunhong CHEN Majid SARRAFZADEH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2673-2680 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: gate duplication, logic synthesis, delay optimization, technology mapping,
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Functional Decomposition with Application to LUT-Based FPGA Synthesis Jian QIAO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/08/01 Vol. E84-A No. 8 ; pp. 2004-2013 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic synthesis, functional decomposition, compatibility class encoding, LUT-based FPGAs,
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A Specification Style of Four-Phase Handshaking Asynchronous Controllers and the Optimization of Its Return-to-Zero Phase Rafael K. MORIZAWA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2446-2455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Methodology Keyword: asynchronous circuit, asynchronous specification, logic synthesis, CAD tool,
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Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm Barry SHACKLEFORD Etsuko OKUSHI Mitsuhiro YASUDA Hisao KOIZUMI Katsuhiko SEO Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2528-2537 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: genetic algorithm, logic synthesis, hardware acceleration,
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A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks Yu-Liang WU Wangning LONG Hongbing FAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/25 Vol. E83-A No. 6 ; pp. 1131-1137 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: rewiring, logic synthesis, circuit minimization, redundancy,
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Logic Minimization for Large-Scale Networks Based on Multi-Signal Implications Masayuki YUGUCHI Kazutoshi WAKABAYASHI Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 ; pp. 2390-2397 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic synthesis, logic minimization, implication, implication graph,
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Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions Takashi HIRAYAMA Goro KODA Yasuaki NISHITANI Kensuke SHIMIZU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/09/25 Vol. E82-D No. 9 ; pp. 1278-1286 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: logic synthesis, exclusive-or, single stuck-at fault, easily testable realization,
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Comparison of Logic Operators for Use in Multiple-Valued Sum-of-Products Expressions Takahiro HOZUMI Osamu KAKUSHO Yutaka HATA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/25 Vol. E82-D No. 5 ; pp. 933-939 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications) Category: Logic Design Keyword: logic synthesis, cost reduction, two-level circuits, sum-of-products expression, Shannon expansion,
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Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams Gueesang LEE Sungju PARK
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 ; pp. 1820-1825 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic synthesis, FPGA, Cellular architetcture, Maitra terms, ETDO,
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An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization Kang YI Seong Yong OHM Chu Shik JHON
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 ; pp. 1807-1812 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic synthesis, technology mapping, logic minimization, Boolean network, field-programmable gate array,
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Minimization of AND-EXOR Expressions for Symmetric Functions Takashi HIRAYAMA Yasuaki NISHITANI Kensuke SHIMIZU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 ; pp. 567-570 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: logic synthesis, AND-EXOR expression, symmetric function, logic minimization algorithm,
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Synthesis of Asynchronous Circuits from Signal Transition Graph Specifications Sung-Bum PARK Takashi NANYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/03/25 Vol. E80-D No. 3 ; pp. 326-335 Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design) Category: Synthesis Keyword: asynchronous synthesis, logic synthesis, signal transition graphs, Petri nets, speed-independent circuits,
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Power and Area Minimization by Reorganizing CMOS Complex-Gates Masayoshi TACHIBANA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 ; pp. 312-320 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: VLSI CAD, logic synthesis, complex-gate, transistor sizing,
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Implicit Representation and Manipulation of Binary Decision Diagrams Hitoshi YAMAUCHI Nagisa ISHIURA Hiromitsu TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 ; pp. 354-362 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: binary decision diagram (BDD), representation of Boolean functions, logic design verification, logic synthesis, implicit representation of graphs,
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A Local Cover Technique for the Minimization of Multiple-Valued Input Binary-Valued Output Functions Giuseppe CARUSO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/01/25 Vol. E79-A No. 1 ; pp. 110-117 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: Boolean function with multiple-valued inputs, logic synthesis, logic minimization,
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Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I Satoshi YOKOTA Hiroyuki KANBARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 ; pp. 1742-1748 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware description language, conformance test, logic synthesis, UDL/I,
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Phase Optimization in Technology Mapping Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 ; pp. 1735-1741 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic synthesis, technology mapping, phase optimization, binary decision diagrams,
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Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 ; pp. 861-867 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: retiming, logic synthesis, redundancy removal, test synthesis,
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Network Hierarchies and Node Minimization Robert K. BRAYTON Ellen M. SENTOVICH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 ; pp. 199-208 Type of Manuscript: INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, logic optimization, don't cares, Boolean relations, nondeterministic finite automata,
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A New Algorithm for Boolean Matching Utilizing Structural Information Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 ; pp. 219-223 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, technology mapping, Boolean matching, binary decision diagrams,
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Optimization of Sequential Synchronous Digital Circuits Using Structural Models Giovanni De MICHELI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1018-1029 Type of Manuscript: INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: computer hardware and disign, synchronous circuits, CAD, logic synthesis,
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Coherent Optimisation Strategies for Multilevel Synthesis Khalid SAKOUTI Pierre ABOUZEID Michel CRASTES Thierry BESSON Jerome FRON Gabrièle SAUCIER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1093-1101 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: computer-hardware and design, logic synthesis,
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Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1085-1092 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, binary decision diagrams, combinational circuits,
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Analysis of the Trends in Logic Synthesis Gabrièle SAUCIER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1006-1017 Type of Manuscript: INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, algebraic factorization, binary decision diagrams,
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Fast Generation of Prime-Irredundant Covers from Binary Decision Diagrams Shin-ichi MINATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/25 Vol. E76-A No. 6 ; pp. 967-973 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: BDDs (Binary Decision Diagrams), prime-irredundant covers, Boolean functions, sum-of-products forms, logic synthesis,
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Timing Optimization of Multi-Level Networks Using Boolean Relations Yuji KUKIMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/03/25 Vol. E76-A No. 3 ; pp. 362-369 Type of Manuscript: Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems) Category: Keyword: timing optimization, logic synthesis, logic optimization, Boolean relations, Boolean unification,
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Applications of Boolean Unification to Combinational Logic Synthesis Yuji KUKIMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 ; pp. 1212-1219 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: Boolean unification, Boolean equations, logic synthesis, logic optimization, Boolean relations,
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Minimum-Width Method of Variable Ordering for Binary Decision Diagrams Shin-ichi MINATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 ; pp. 392-399 Type of Manuscript: Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: binary decision diagrams, boolean function, logic synthesis, variable ordering,
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