Keyword : logic synthesis


Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1374-1380
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
logic synthesistechnology mappingFPGASAT
 Summary | Full Text:PDF(223.5KB)

Synthesis Algorithm for Parallel Index Generator
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2451-2458
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
logic synthesisindex generation function
 Summary | Full Text:PDF(502.1KB)

Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm
Ming-Chih CHEN Shen-Fu HSIAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3221-3228
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
AESVLSIcommon subexpression elimination (CSE)information securitylogic synthesis
 Summary | Full Text:PDF(1009KB)

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams
Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1 ; pp. 257-266
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic synthesisdual-railRSFQbinary decision diagrams (BDDs)
 Summary | Full Text:PDF(462.9KB)

Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3443-3450
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesisBoolean matchingcell-library bindingtechnology mappingcanonical form
 Summary | Full Text:PDF(326.9KB)

Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition
Masao MORIMOTO Yoshinori TANAKA Makoto NAGATA Kazuo TAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3324-3331
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesisASDDLasymmetric slopedifferential logichigh speed
 Summary | Full Text:PDF(726.6KB)

An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD
Tomonori IZUMI Shin'ichi KOUYAMA Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 907-914
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
reconfigurable systemdesign technologylogic synthesisvariable orderinglook-up table
 Summary | Full Text:PDF(2.1MB)

Timing Optimization Methodology Based on Replacing Flip-Flops by Latches
Ko YOSHIKAWA Keisuke KANAMARU Yasuhiko HAGIHARA Shigeto INUI Yuichi NAKAMURA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3151-3158
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesissequential circuittiming optimizationlevel-sensitive latchformal verification
 Summary | Full Text:PDF(402.1KB)

Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser
Naohiko SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3225-3229
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword: 
logic synthesisHDL conversionSFLverilog
 Summary | Full Text:PDF(266.3KB)

Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design
Nattha SRETASEREEKUL Hiroshi SAITO Euiseok KIM Metehan OZCAN Masashi IMAI Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3028-3037
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
asynchronous controllerslogic synthesisControl Data Flow Graphs (CDFGs)Signal Transition Graphs (STGs)
 Summary | Full Text:PDF(801.7KB)

An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2715-2724
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
functional decompositionBDDslogic synthesisFPGA
 Summary | Full Text:PDF(295.2KB)

Accelerating Logic Rewiring Using Implication Analysis Tree
Chin-Ngai SZE Wangning LONG Yu-Liang WU Jinian BIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2725-2736
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
alternative wirelogic transformationlogic synthesis
 Summary | Full Text:PDF(433.7KB)

Modular Synthesis of Timed Circuits Using Partial Order Reduction
Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2684-2692
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesispartial order reductiontimed circuitsmodular synthesis
 Summary | Full Text:PDF(568.5KB)

Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications
Shih-Chieh CHANG Zhong-Zhen WU Sheng-Hong TU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/12/01
Vol. E84-A  No. 12 ; pp. 3116-3124
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic synthesisredundant wirealternative wiremandatory assignmentlayout synthesis
 Summary | Full Text:PDF(341.1KB)

Generalized Reasoning Scheme for Redundancy Addition and Removal
Jose Alberto ESPEJO Luis ENTRENA Enrique San MILLAN Celia LOPEZ 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2665-2672
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
redundancy addition and removalrewiringlogic synthesisstructural methods
 Summary | Full Text:PDF(860.5KB)

LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression
Hiroshi TSUTSUI Akihiko TOMITA Shigenori SUGIMOTO Kazuhisa SAKAI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2681-2689
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: FPGA Systhesis
Keyword: 
reconfigurable logicprogrammable logicsystem architecture and designlogic synthesissum of products
 Summary | Full Text:PDF(691.5KB)

Timing Driven Gate Duplication in Technology Independent Phase
Ankur SRIVASTAVA Chunhong CHEN Majid SARRAFZADEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2673-2680
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
gate duplicationlogic synthesisdelay optimizationtechnology mapping
 Summary | Full Text:PDF(431.5KB)

Functional Decomposition with Application to LUT-Based FPGA Synthesis
Jian QIAO Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8 ; pp. 2004-2013
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic synthesisfunctional decompositioncompatibility class encodingLUT-based FPGAs
 Summary | Full Text:PDF(1.2MB)

A Specification Style of Four-Phase Handshaking Asynchronous Controllers and the Optimization of Its Return-to-Zero Phase
Rafael K. MORIZAWA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2446-2455
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword: 
asynchronous circuitasynchronous specificationlogic synthesisCAD tool
 Summary | Full Text:PDF(544.3KB)

Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
Barry SHACKLEFORD Etsuko OKUSHI Mitsuhiro YASUDA Hisao KOIZUMI Katsuhiko SEO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2528-2537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
genetic algorithmlogic synthesishardware acceleration
 Summary | Full Text:PDF(1.1MB)

A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
Yu-Liang WU Wangning LONG Hongbing FAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1131-1137
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
rewiringlogic synthesiscircuit minimizationredundancy
 Summary | Full Text:PDF(895.7KB)

Logic Minimization for Large-Scale Networks Based on Multi-Signal Implications
Masayuki YUGUCHI Kazutoshi WAKABAYASHI Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2390-2397
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesislogic minimizationimplicationimplication graph
 Summary | Full Text:PDF(613.5KB)

Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions
Takashi HIRAYAMA Goro KODA Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/09/25
Vol. E82-D  No. 9 ; pp. 1278-1286
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
logic synthesisexclusive-orsingle stuck-at faulteasily testable realization
 Summary | Full Text:PDF(861.2KB)

Comparison of Logic Operators for Use in Multiple-Valued Sum-of-Products Expressions
Takahiro HOZUMI Osamu KAKUSHO Yutaka HATA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5 ; pp. 933-939
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Logic Design
Keyword: 
logic synthesiscost reductiontwo-level circuitssum-of-products expressionShannon expansion
 Summary | Full Text:PDF(928.7KB)

Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams
Gueesang LEE Sungju PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1820-1825
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesisFPGACellular architetctureMaitra termsETDO
 Summary | Full Text:PDF(423.5KB)

An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI Seong Yong OHM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1807-1812
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappinglogic minimizationBoolean networkfield-programmable gate array
 Summary | Full Text:PDF(534.1KB)

Minimization of AND-EXOR Expressions for Symmetric Functions
Takashi HIRAYAMA Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 567-570
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
logic synthesisAND-EXOR expressionsymmetric functionlogic minimization algorithm
 Summary | Full Text:PDF(351.3KB)

Synthesis of Asynchronous Circuits from Signal Transition Graph Specifications
Sung-Bum PARK Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/03/25
Vol. E80-D  No. 3 ; pp. 326-335
Type of Manuscript:  Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Synthesis
Keyword: 
asynchronous synthesislogic synthesissignal transition graphsPetri netsspeed-independent circuits
 Summary | Full Text:PDF(834.8KB)

Power and Area Minimization by Reorganizing CMOS Complex-Gates
Masayoshi TACHIBANA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 312-320
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
VLSI CADlogic synthesiscomplex-gatetransistor sizing
 Summary | Full Text:PDF(798.2KB)

Implicit Representation and Manipulation of Binary Decision Diagrams
Hitoshi YAMAUCHI Nagisa ISHIURA Hiromitsu TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 354-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagram (BDD)representation of Boolean functionslogic design verificationlogic synthesisimplicit representation of graphs
 Summary | Full Text:PDF(747KB)

A Local Cover Technique for the Minimization of Multiple-Valued Input Binary-Valued Output Functions
Giuseppe CARUSO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/01/25
Vol. E79-A  No. 1 ; pp. 110-117
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Boolean function with multiple-valued inputslogic synthesislogic minimization
 Summary | Full Text:PDF(615.3KB)

Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I
Satoshi YOKOTA Hiroyuki KANBARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1742-1748
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description languageconformance testlogic synthesisUDL/I
 Summary | Full Text:PDF(621.1KB)

Phase Optimization in Technology Mapping
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1735-1741
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappingphase optimizationbinary decision diagrams
 Summary | Full Text:PDF(514.1KB)

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement
Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 861-867
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
retiminglogic synthesisredundancy removaltest synthesis
 Summary | Full Text:PDF(542.1KB)

Network Hierarchies and Node Minimization
Robert K. BRAYTON Ellen M. SENTOVICH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 199-208
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesislogic optimizationdon't caresBoolean relationsnondeterministic finite automata
 Summary | Full Text:PDF(1MB)

A New Algorithm for Boolean Matching Utilizing Structural Information
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 219-223
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesistechnology mappingBoolean matchingbinary decision diagrams
 Summary | Full Text:PDF(380.7KB)

Optimization of Sequential Synchronous Digital Circuits Using Structural Models
Giovanni De MICHELI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1018-1029
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
computer hardware and disignsynchronous circuitsCADlogic synthesis
 Summary | Full Text:PDF(988.2KB)

Coherent Optimisation Strategies for Multilevel Synthesis
Khalid SAKOUTI Pierre ABOUZEID Michel CRASTES Thierry BESSON Jerome FRON Gabrièle SAUCIER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1093-1101
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
computer-hardware and designlogic synthesis
 Summary | Full Text:PDF(673.5KB)

Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams
Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1085-1092
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesisbinary decision diagramscombinational circuits
 Summary | Full Text:PDF(647.1KB)

Analysis of the Trends in Logic Synthesis
Gabrièle SAUCIER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1006-1017
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesisalgebraic factorizationbinary decision diagrams
 Summary | Full Text:PDF(829.1KB)

Fast Generation of Prime-Irredundant Covers from Binary Decision Diagrams
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6 ; pp. 967-973
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
BDDs (Binary Decision Diagrams)prime-irredundant coversBoolean functionssum-of-products formslogic synthesis
 Summary | Full Text:PDF(531.1KB)

Timing Optimization of Multi-Level Networks Using Boolean Relations
Yuji KUKIMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3 ; pp. 362-369
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
timing optimizationlogic synthesislogic optimizationBoolean relationsBoolean unification
 Summary | Full Text:PDF(696.8KB)

Applications of Boolean Unification to Combinational Logic Synthesis
Yuji KUKIMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1212-1219
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Boolean unificationBoolean equationslogic synthesislogic optimizationBoolean relations
 Summary | Full Text:PDF(648.3KB)

Minimum-Width Method of Variable Ordering for Binary Decision Diagrams
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 392-399
Type of Manuscript:  Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagramsboolean functionlogic synthesisvariable ordering
 Summary | Full Text:PDF(616.5KB)