Keyword : logic minimization


A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix
Tsutomu SASAO Yuta URANO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2427-2433
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
minimal coverlinear transformationfunctional decompositionincompletely specified functionlogic minimization
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A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits
Takashi HIRAYAMA Hayato SUGAWARA Katsuhisa YAMANAKA Yasuaki NISHITANI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2253-2261
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Reversible/Quantum Computing
Keyword: 
reversible logic circuitsToffoli gateslower boundlogic minimization
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A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5 ; pp. 932-940
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
three-level networksAND-EXORNP-equivalencecoordinate representationµ-equivalencespectral methodlogic minimization
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Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1492-1500
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
three-level networklogic minimizationadderprogrammable logic
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Logic Minimization for Large-Scale Networks Based on Multi-Signal Implications
Masayuki YUGUCHI Kazutoshi WAKABAYASHI Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2390-2397
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesislogic minimizationimplicationimplication graph
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Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization
Kazuyoshi TAKAGI Hiroshi HATAKEDA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2407-2413
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Free BDDPass-Transistor LogicBoolean functionlogic minimization
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AND/OR Reasoning Graphs for Determining Prime Implicants in Multi-Level Combinational Networks*
Dominik STOFFEL Wolfgang KUNZ Stefan GERBER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/12/25
Vol. E80-A  No. 12 ; pp. 2581-2588
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
switching theorymulti-level synthesislogic minimizationprime implicantsgraph representationAND/OR graphs
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Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10 ; pp. 1001-1008
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
three-level networksAND-EXORlogic minimizationcomplexity of logic networksNP-equivalence
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An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI Seong Yong OHM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1807-1812
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappinglogic minimizationBoolean networkfield-programmable gate array
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Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm
Tsutomu SASAO Debatosh DEBNATH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2123-2130
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
AND-EXORReed-Muller expressioncomplexity of logic networkslogic minimizationbinary decision diagramseasily testable networks
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A Local Cover Technique for the Minimization of Multiple-Valued Input Binary-Valued Output Functions
Giuseppe CARUSO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/01/25
Vol. E79-A  No. 1 ; pp. 110-117
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Boolean function with multiple-valued inputslogic synthesislogic minimization
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Lower Bounds on Size of Periodic Functions in Exclusive-OR Sum-of-Products Expressions
Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3 ; pp. 475-482
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Computer Aided Design (CAD)
Keyword: 
exclusive-OR sum-of-productssize of circuitslower boundlogic minimizationlogic design
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Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams
Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5 ; pp. 562-570
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Logic Design
Keyword: 
Reed-Muller expressionAND-EXOR expressionlogic minimizationbinary decision diagramsymmetric functions
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