Keyword : logic circuit optimization


Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design
Norio OHKUBO Takeo YAMASHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 618-623
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
delay calculationeffective capacitancelogic circuit optimizationdelay optimizationLSI design
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