An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines Nobutaro SHIBATAMitsuo NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/02/25 Vol. E79-ANo. 2 ;
pp. 210-216 Type of Manuscript: Special Section PAPER (Special Section on Analog Technologies in Submicron Era) Category: Keyword: subranging A/D converter, coarse conversion, fine conversion, linearity error,