Keyword : linearity error

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines
Nobutaro SHIBATA Mitsuo NAKAMURA 
Publication:   
Publication Date: 2018/08/01
Vol. E101-A  No. 8 ; pp. 1185-1196
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ATE, delay-locked loop, digital-to-time converter, linearity error, on the fly, plain CMOS logic, timing jitter, timing vernier, 
 Summary | Full Text:PDF
Static Linearity Error Analysis of Subranging A/D Converters
Takashi OKUDA Toshio KUMAMOTO Masao ITO Takahiro MIKI Keisuke OKADA Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/02/25
Vol. E79-A  No. 2 ; pp. 210-216
Type of Manuscript:  Special Section PAPER (Special Section on Analog Technologies in Submicron Era)
Category: 
Keyword: 
subranging A/D converter, coarse conversion, fine conversion, linearity error, 
 Summary | Full Text:PDF