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| Keyword : leakage power
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Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
Kyundong KIM Seidai TAKEDA Shinobu MIWA Hiroshi NAKAMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12 ;
pp. 2301-2308
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword:
low-power, cache, leakage power, | | | Summary | Full Text:PDF(1.6MB) | |
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Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model
Seidai TAKEDA Kyundong KIM Hiroshi NAKAMURA Kimiyoshi USAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12 ;
pp. 2499-2509
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
power gating, MTCMOS, delay, leakage power, | | | Summary | Full Text:PDF(2MB) | |
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A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM
Tadayoshi ENOMOTO Nobuaki KOBAYASHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C
No. 4 ;
pp. 530-538
Type of Manuscript:
Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category:
Keyword:
SRAM, leakage power, “write” margin, “read” margin, | | | Summary | Full Text:PDF(1.4MB) | |
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A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
How-Rern LIN Wei-Hao CHIU Tsung-Yi WU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C
No. 4 ;
pp. 386-390
Type of Manuscript:
Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category:
Keyword:
leakage power, leakage tolerance, high performance, domino logic, | | | Summary | Full Text:PDF(291.3KB) | |
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Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits
Naoaki OHKUBO Kimiyoshi USAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12 ;
pp. 3482-3490
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword:
MTCMOS, selective-MT, static timing analysis, leakage power, delay modeling, | | | Summary | Full Text:PDF(1.1MB) | |
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Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power
Kimiyoshi USAMI Hiroshi YOSHIOKA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A
No. 12 ;
pp. 3116-3123
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
leakage power, scaling, active leakage, burn-in, MTCMOS, | | | Summary | Full Text:PDF(1.1MB) | |
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