| Keyword : layout
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The Effect of Device Layout Schemes on RF Performance of Multi-Finger MOSFETs Yongho OH Jae-Sung RIEH | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C
No. 5 ;
pp. 785-791
Type of Manuscript:
Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Keyword: fT, fmax, gate resistance, layout, RF MOSFET, | | Summary | Full Text:PDF | |
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A Cell Synthesis Method for Salicide Process Using Assignment Graph Kazuhisa OKADA Takayuki YAMANOUCHI Takashi KAMBE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12 ;
pp. 2577-2583
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis Keyword: cell, layout, synthesis, salicide, assignment graph, | | Summary | Full Text:PDF | |
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A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays Hiroshi SHIROTA Satoshi SHIBATANI Masayuki TERAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A
No. 3 ;
pp. 506-513
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: Keyword: multilayer routing, layout, CAD, VLSI, | | Summary | Full Text:PDF | |
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A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A
No. 3 ;
pp. 321-329
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: Keyword: FPGA, technology mapping, layout, path delay, performance optimization, | | Summary | Full Text:PDF | |
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