IEICE Trans

Keyword : layout

Method for Consistent GUI Arrangements by Analyzing Existing Windows and Its Evaluation Junko SHIROGANE Seitaro SHIRAI Hajime IWATA Yoshiaki FUKAZAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/05/01 Vol. E97-D No. 5 ; pp. 1084-1096 Type of Manuscript: Special Section PAPER (Special Section on Knowledge-Based Software Engineering) Category: Keyword: GUI, usability, consistency, layout,
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Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration Tsang-Chi KAN Ying-Jung CHEN Hung-Ming HONG Shanq-Jang RUAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/02/01 Vol. E97-A No. 2 ; pp. 597-605 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: design for manufacturability (DFM), layout, redundant via, standard cell (SC),
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The Effect of Device Layout Schemes on RF Performance of Multi-Finger MOSFETs Yongho OH Jae-Sung RIEH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/05/01 Vol. E95-C No. 5 ; pp. 785-791 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: f_T, f_max, gate resistance, layout, RF MOSFET,
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An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability Koichi HAMAMOTO Hiroshi FUKETA Masanori HASHIMOTO Yukio MITSUYAMA Takao ONOYE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/02/01 Vol. E92-C No. 2 ; pp. 281-285 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: body bias, layout,
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Voltage Island Generation in Cell Based Dual-Vdd Design Yici CAI Bin LIU Qiang ZHOU Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 ; pp. 267-273 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dual-Vdd, layout, placement, voltage island, voltage assignment,
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Linear Layout of the Supercube Jywe-Fei FANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/02/01 Vol. E89-D No. 2 ; pp. 779-782 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science) Category: Network Keyword: interconnection networks, supercubes, layout, embedding in books,
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A Timing Driven Crosstalk Optimizer for Gridded Channel Routing Shih-Hsu HUANG Yi-Siang HSU Chiu-Cheng LIN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/06/01 Vol. E87-D No. 6 ; pp. 1575-1581 Type of Manuscript: LETTER Category: Computer Components Keyword: layout, gridded channel routing, crosstalk minimization, delay degradation, relative signal arrival time,
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Recognition of Floorplan by Parametric BSG for Reuse of Layout Design Keishi SAKANUSHI Zhonglin WU Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 ; pp. 872-879 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: parametric BSG, layout, reuse, floorplan, technology migration,
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Reducing Wire Lengths in the Layout of Cyclic Shifters Peter-Michael SEIDEL Mark A. HILLEBRAND Thomas SCHURGER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2714-2721 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Keyword: cyclic shifter, layout, wire length, wire delay,
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Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture Tomonori IZUMI Ryuji KAN Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2538-2544 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: plastic cell architecture, reconfigurable logic, technology mapping, layout,
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A Cell Synthesis Method for Salicide Process Using Assignment Graph Kazuhisa OKADA Takayuki YAMANOUCHI Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2577-2583 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Synthesis Keyword: cell, layout, synthesis, salicide, assignment graph,
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A GSM900/DCS1800 Dual-Band MMIC Power Amplifier Using Outside-Base/Center-Via-Hole Layout Multifinger HBT Kazutomi MORI Kenichiro CHOUMEI Teruyuki SHIMURA Tadashi TAKAGI Yukio IKEDA Osami ISHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/11/25 Vol. E82-C No. 11 ; pp. 1913-1920 Type of Manuscript: Special Section PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century) Category: RF Power Devices Keyword: microwave, amplifier, efficiency, layout, heterojunction bipolar transistor, multifinger,
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Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan Tomonori IZUMI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 ; pp. 857-865 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: floorplan, layout, area optimization, air-pressure, zero-wasted-area,
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An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology Takumi WATANABE Yusuke OHTOMO Kimihiro YAMAKOSHI Yuichiro TAKEI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/04/25 Vol. E81-A No. 4 ; pp. 677-684 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: routing methodology, maze router, layout, CAD, VLSI,
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A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays Hiroshi SHIROTA Satoshi SHIBATANI Masayuki TERAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 ; pp. 506-513 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: multilayer routing, layout, CAD, VLSI,
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A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs Shigeki TOMISHIMA Shigehiro KUGE Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 ; pp. 808-811 Type of Manuscript: Special Section LETTER (Special Issue on ULSI Memory Technology) Category: Dynamic RAMs Keyword: memory, triple metal, source line, layout,
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A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 ; pp. 321-329 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: FPGA, technology mapping, layout, path delay, performance optimization,
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Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization Masaaki YAMADA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Takashi MITSUHASHI Nobuyuki GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/25 Vol. E78-C No. 4 ; pp. 441-446 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: DA/Architecture Keyword: LSI, layout, transistor sizing, low power, CAD,
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A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm Tadanao TSUBOTA Masahiro KAWAKITA Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/25 Vol. E78-A No. 3 ; pp. 345-352 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: branch-and-bound, layout, global routing, channel-intersection graph, analog, LSI, CAD,
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Linking Register-Transfer and Physical Levels of Design Fadi J. KURDAHI Daniel D. GAJSKI Champaka RAMACHANDRAN Viraphol CHAIYAKUL
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 991-1005 Type of Manuscript: INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Design Keyword: layout, area, delay, estimation, high-level design,
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Cell Designer: An Automatic Placement and Routing Tool for the Mixed Design of Macro and Standard Cells Young Seok BAEK Byoung Yoon CHEON Kyung Sik KIM Hyun Chan LEE Chul Dong LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/02/25 Vol. E75-A No. 2 ; pp. 224-232 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: VLSI/CAD, layout, placement, routing, macro cell, standard cell,
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