Keyword : latency


A QoS-Aware Dual Crosspoint Queued Switch with Largest Weighted Occupancy First Scheduling Algorithm
Gordana GARDASEVIC Soko DIVANOVIC Milutin RADONJIC Igor RADUSINOVIC 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2015/01/01
Vol. E98-B  No. 1 ; pp. 201-208
Type of Manuscript:  PAPER
Category: Network
Keyword: 
Dual Crosspoint Queued switchQuality of ServiceLargest Weighted Occupancy First scheduling algorithmlatencycell loss probability
 Summary | Full Text:PDF(1.1MB)

Implementation of the Complete Predictor for DDR3 SDRAM
Vladimir V. STANKOVIC Nebojsa Z. MILENKOVIC Oliver M. VOJINOVIC 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3 ; pp. 589-592
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
DDR3 SDRAMlatencypredictor
 Summary | Full Text:PDF(158.8KB)

A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver
Joohyun LEE Bontae KOO Hyuckjae LEE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/05/01
Vol. E96-B  No. 5 ; pp. 1089-1096
Type of Manuscript:  PAPER
Category: Transmission Systems and Transmission Equipment for Communications
Keyword: 
LTEuplinkrandom accessPRACHlatencythroughput
 Summary | Full Text:PDF(1.6MB)

An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation
Minoru IIZUKA Naohiro HAMADA Hiroshi SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 482-491
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuits with bundled-data implementationlatencyASICand design support tool
 Summary | Full Text:PDF(1.6MB)

MAC 2: A Multi-Hop Adaptive MAC Protocol with Packet Concatenation for Wireless Sensor Networks
Kien NGUYEN Ulrich MEIS Yusheng JI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 480-489
Type of Manuscript:  Special Section PAPER (Special Section on Architectures, Protocols, and Applications for the Future Internet)
Category: 
Keyword: 
multi-hop MACenergy efficientlatencythroughput
 Summary | Full Text:PDF(381.6KB)

Shaka: User Movement Estimation Considering Reliability, Power Saving, and Latency Using Mobile Phone
Arei KOBAYASHI Shigeki MURAMATSU Daisuke KAMISAKA Takafumi WATANABE Atsunori MINAMIKAWA Takeshi IWAMOTO Hiroyuki YOKOYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/06/01
Vol. E94-D  No. 6 ; pp. 1153-1163
Type of Manuscript:  Special Section PAPER (Special Section on Emerging Technologies of Ubiquitous Computing Systems)
Category: 
Keyword: 
activity recognitionaccelerometermicrophoneGPSreliabilitypower savinglatency
 Summary | Full Text:PDF(2.3MB)

Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip
Guang SUN Shijun LIN Depeng JIN Yong LI Li SU Yuanyuan ZHANG Lieguang ZENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/05/01
Vol. E94-D  No. 5 ; pp. 1000-1007
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
mapping algorithmnetwork on chipenergy consumptionlatencybandwidth
 Summary | Full Text:PDF(603.4KB)

DDR3 SDRAM with a Complete Predictor
Vladimir V. STANKOVIC Nebojsa Z. MILENKOVIC 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/09/01
Vol. E93-D  No. 9 ; pp. 2635-2638
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
DDR3 SDRAMlatencypredictor
 Summary | Full Text:PDF(185.9KB)

Frame Resource Allocation Schemes that Improve System Capacity and Latency Performance of Time-Division Duplex Multihop Relay Systems
Youhei OHNO Tatsuya SHIMIZU Takefumi HIRAGURI Masashi NAKATSUGAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/08/01
Vol. E93-B  No. 8 ; pp. 2035-2042
Type of Manuscript:  Special Section PAPER (Special Section on Implementation, Experiments, and Practice for Ad Hoc and Mesh Networks)
Category: 
Keyword: 
multihop relayframe resource allocationsystem capacitylatency
 Summary | Full Text:PDF(1.6MB)

A Dual-Port Access Structure of 3D Mesh-Based NoC
Yuanyuan ZHANG Shijun LIN Li SU Depeng JIN Lieguang ZENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/07/01
Vol. E93-D  No. 7 ; pp. 1987-1990
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
3D mesh-based NoCdual-port access structurelatencythroughputarea overhead
 Summary | Full Text:PDF(151.3KB)

DRAM Controller with a Complete Predictor
Vladimir V. STANKOVIC Nebojsa Z. MILENKOVIC 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/04/01
Vol. E92-D  No. 4 ; pp. 584-593
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
DRAMlatencyDRAM controllerpredictor
 Summary | Full Text:PDF(422.3KB)

Utilizing a Perceptive Technique for the Delay-Sensitive Scheduling in Wireless Sensor Networks
Deepesh Man SHRESTHA Changsu SUH Young-Bae KO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/12/01
Vol. E91-B  No. 12 ; pp. 4017-4019
Type of Manuscript:  LETTER
Category: Network
Keyword: 
carrier sensingwireless sensor networkslatencyenergy
 Summary | Full Text:PDF(172.2KB)

Power and Skew Aware Point Diffusion Clock Network
Gunok JUNG Chunghee KIM Kyoungkuk CHAE Giho PARK Sung Bae PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/11/01
Vol. E91-C  No. 11 ; pp. 1832-1834
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
clock networkskewlatencylow power
 Summary | Full Text:PDF(868KB)

Reduced Congestion Queuing: QoS Support for Optimizing Base Station Layout in Multihop Wireless Networks
Akira TANAKA Susumu YOSHIDA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/11/01
Vol. E91-B  No. 11 ; pp. 3779-3783
Type of Manuscript:  LETTER
Category: Terrestrial Radio Communications
Keyword: 
multihop wireless networkdelaypriority controlbase station densityjitterlatency
 Summary | Full Text:PDF(1.2MB)

Design Methodology of a Sensor Network Architecture Supporting Urgent Information and Its Evaluation
Tetsuya KAWAI Naoki WAKAMIYA Masayuki MURATA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/10/01
Vol. E91-B  No. 10 ; pp. 3232-3240
Type of Manuscript:  PAPER
Category: Network
Keyword: 
sensor networksurgent informationlatencyreliability
 Summary | Full Text:PDF(677.9KB)

Analytical Model for Burstification Latency in Optical Burst Switched Networks
Yuhua CHEN Pramode K. VERMA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/09/01
Vol. E90-B  No. 9 ; pp. 2588-2591
Type of Manuscript:  LETTER
Category: Switching for Communications
Keyword: 
optical switchingoptical burst switchingwavelength division multiplexing (WDM)latency
 Summary | Full Text:PDF(296KB)

Latency-Aware Bus Arbitration for Real-Time Embedded Systems
Minje JUN Kwanhu BANG Hyuk-Jun LEE Eui-Young CHUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/03/01
Vol. E90-D  No. 3 ; pp. 676-679
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
latencyarbiterQoSperformancebusslack
 Summary | Full Text:PDF(297.4KB)

Low Latency and Memory Efficient Viterbi Decoder Using Modified State-Mapping Method
Sang-Ho SEO Hae-Wook CHOI Sin-Chong PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/04/01
Vol. E89-B  No. 4 ; pp. 1413-1416
Type of Manuscript:  LETTER
Category: Fundamental Theories for Communications
Keyword: 
Viterbi decoderregister exchangetrace backlatencyresource usage
 Summary | Full Text:PDF(977.8KB)

Evaluation of Cognitive Function Using Event-Related Potential (P300 and CNV): Comparison among Young, Middle-Aged, and Elderly People
Atsuo MURATA Takashi SORA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/04/01
Vol. E87-D  No. 4 ; pp. 992-996
Type of Manuscript:  PAPER
Category: Rehabilitation Engineering and Assistive Technology
Keyword: 
P300CNVaginglatencyamplitude
 Summary | Full Text:PDF(423.5KB)

Efficient Telescopic Search Motion-Estimation Architecture Based on Data-Flow Optimization
Wujian ZHANG Runde ZHOU Tsunehachi ISHITANI Ryota KASAI Toshio KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3 ; pp. 390-398
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion estimationtelescopic searchsystolic arraylatencylow-power
 Summary | Full Text:PDF(674KB)

High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1303-1315
Type of Manuscript:  INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
DRAMmemory bottleneckdata bandwidthlatencysynchronous DRAMpipeline architecturedata prefetchingcache DRAMfast copybackRambus interfaceRambus DRAMprotocol packetPLL
 Summary | Full Text:PDF(983.9KB)

Mixed Mode Circuit Simulation Using Dynamic Network Separation and Selective Trace
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3 ; pp. 454-460
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Modeling and Simulation
Keyword: 
mixed mode circuit simulationdynamic partitioningnetwork separationlatencyselective trace
 Summary | Full Text:PDF(528.9KB)

Relaxation-Based Circuit Simulation Techniques in the Frequency Domain
Hiroaki MAKINO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4 ; pp. 626-630
Type of Manuscript:  PAPER
Category: Modeling and Simulation
Keyword: 
harmonic balancerelaxationcircuit simulationlatencyfrequency domain
 Summary | Full Text:PDF(388.8KB)

Mixed Mode Circuit Simulation Using Dynamic Partitioning
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3 ; pp. 292-298
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
circuit simulationmixed mode simulationdynamic partitioninghierarchical decompositionlatency
 Summary | Full Text:PDF(620.8KB)

Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation
Makoto HONDA Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 455-462
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued MOS current-mode circuitresidue number systemlatencyparallel processingrobot vision
 Summary | Full Text:PDF(737.7KB)

Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 347-351
Type of Manuscript:  Special Section LETTER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
circuit simulation network tearinghierarchical decompositionlatency
 Summary | Full Text:PDF(262.3KB)