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| Keyword : jitter
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A Jitter Insertion and Accumulation Model for Clock Repeaters
Monica FIGUEIREDO Rui L. AGUIAR | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12 ;
pp. 2430-2442
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
jitter, noise, CMOS clock repeaters, | | | Summary | Full Text:PDF | |
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Robust Scheduling Scheme to Reduce Queue Length Fluctuation in Streaming Services
Hyun Jong KIM Seong Gon CHOI | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2011/05/01
Vol. E94-B
No. 5 ;
pp. 1452-1455
Type of Manuscript:
LETTER
Category: Network
Keyword:
scheduling, AQM, DiffServ, QoS, jitter, IPTV, | | | Summary | Full Text:PDF | |
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Towards a Fairness Multimedia Transmission Using Layered-Based Multicast Protocol
Heru SUKOCO Yoshiaki HORI Hendrawan Kouichi SAKURAI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/11/01
Vol. E93-D
No. 11 ;
pp. 2953-2961
Type of Manuscript:
Special Section PAPER (Special Section on Architectures, Protocols, and Applications for the Future Internet)
Category:
Keyword:
TCP friendly, Receiver-driven Layered Multicast, network simulator, Pareto, quality of service, jitter, throughput, packet loss ratio, fairness, convergence time, | | | Summary | Full Text:PDF | |
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A Supplementary of WiMax Downlink Scheduling for Jitter Sensitive Traffic
Yen-Wen CHEN Ming-Huang TSAI | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2010/10/01
Vol. E93-B
No. 10 ;
pp. 2769-2772
Type of Manuscript:
LETTER
Category: Network
Keyword:
WiMax, QoS scheduling, jitter, | | | Summary | Full Text:PDF | |
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Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design
Wenjian YU Rui SHI Chung-Kuan CHENG | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C
No. 4 ;
pp. 444-452
Type of Manuscript:
Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category:
Keyword:
eye diagram, jitter, lossy transmission line, step response, | | | Summary | Full Text:PDF | |
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Application of Microwave and Millimeter-Wave Circuit Technologies to InGaP-HBT ICs for 40-Gbps Optical Transmission Systems
Ken'ichi HOSOYA Yasuyuki SUZUKI Yasushi AMAMIYA Zin YAMAZAKI Masayuki MAMADA Akira FUJIHARA Masafumi KAWANAKA Shin'ichi TANAKA Shigeki WADA Hikaru HIDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/09/01
Vol. E90-C
No. 9 ;
pp. 1685-1694
Type of Manuscript:
Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology)
Category: Active Devices/Circuits
Keyword:
microwave, millimeter-wave, MMIC, GaAs HBT, optical transmission system, distributed amplifier, frequency doubler, phase shifter, flip flop, jitter, impedance matching, | | | Summary | Full Text:PDF | |
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Control-Invariance of Sampled-Data Hybrid Systems with Clocked Events and Jitters
Yoshiyuki TSUCHIE Toshimitsu USHIO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A
No. 4 ;
pp. 707-714
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
hybrid automaton, jitter, control-invariance, state feedback, | | | Summary | Full Text:PDF | |
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A State Dependent RED: An Enhanced Active Queue Management Scheme for Real-Time Internet Services
Intae RYOO Meehyea YANG | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2006/02/01
Vol. E89-B
No. 2 ;
pp. 614-617
Type of Manuscript:
LETTER
Category: Internet
Keyword:
queue management, state dependent RED, jitter, | | | Summary | Full Text:PDF | |
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A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C
No. 6 ;
pp. 956-963
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
capture range, CCO, CDR, clock and data recovery, false lock, jitter, NRZ, PFD, PLL, VCO, z-domain analysis, | | | Summary | Full Text:PDF | |
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Input-Dependent Sampling-Time Error Effects Due to Finite Clock Slope in MOS Samplers
Naoto HAYASAKA Haruo KOBAYASHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C
No. 6 ;
pp. 1015-1021
Type of Manuscript:
Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
sampling, jitter, MOS switch, track/hold circuit, ADC, | | | Summary | Full Text:PDF | |
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Sampling Jitter and Finite Aperture Time Effects in Wideband Data Acquisition Systems
Haruo KOBAYASHI Kensuke KOBAYASHI Masanao MORIMURA Yoshitaka ONAYA Yuuich TAKAHASHI Kouhei ENOMOTO Hideyuki KOGURE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A
No. 2 ;
pp. 335-346
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
jitter, phase noise, aperture time, aperture window, sampling, equivalent-time sampling, ADC, track/hold circuit, digitizing oscilloscope, | | | Summary | Full Text:PDF | |
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A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
Jun-Young PARK Jin-Ku KANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A
No. 6 ;
pp. 1100-1105
Type of Manuscript:
Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category:
Keyword:
oversampling data recovery, PLL, DLL, jitter, | | | Summary | Full Text:PDF | |
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A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C
No. 7 ;
pp. 1334-1340
Type of Manuscript:
PAPER
Category: Integrated Electronics
Keyword:
PLL, CMOS/SIMOX, VCO, clock, jitter, skew, lock range, | | | Summary | Full Text:PDF | |
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Simulation Study on Multi-Hop Jitter Behavior in Integrated ATM Network with CATV and Internet
Naotoshi ADACHI Shoji KASAHARA Yutaka TAKAHASHI | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1998/12/25
Vol. E81-B
No. 12 ;
pp. 2413-2422
Type of Manuscript:
Special Section PAPER (Special Issue on the Latest Development of Telecommunication Research)
Category: QoS Control and Traffic Control
Keyword:
ATM, CATV, internet, MPEG2, multicast, jitter, | | | Summary | Full Text:PDF | |
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Generation of Low Timing Jitter, Sub-Picosecond Optical Pulses Using a Gain-Switched DFB-LD with CW Light Injection and a Nonlinear Optical Loop Mirror
Hiroshi OHTA Seiji NOGIWA Haruo CHIBA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1998/02/25
Vol. E81-C
No. 2 ;
pp. 166-168
Type of Manuscript:
Special Section LETTER (Special Issue on Ultrashort Optical Pulse Technologies and their Applications)
Category:
Keyword:
pulse compression, fiber, laser, jitter, gain-switching, | | | Summary | Full Text:PDF | |
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Optimal Loop Bandwidth Design for Low Noise PLL Applications
Kyoohyun LIM Seung Hee CHOI Beomsup KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10 ;
pp. 1979-1985
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
optimal bandwidth, PLL, jitter, low noise, | | | Summary | Full Text:PDF | |
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A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors
Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12 ;
pp. 1951-1956
Type of Manuscript:
Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword:
electronic circuits, clock generator, PLL, frequency multiplication, VCO, VCO gain, jitter, pull-in range, CMOS, VSP, | | | Summary | Full Text:PDF | |
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