Keyword : irreducible trinomial


Low-Latency Bit-Parallel Systolic Multiplier for Irreducible xm + xn + 1 with GCD(m,n) = 1
Chiou-Yng LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/11/01
Vol. E86-A  No. 11 ; pp. 2844-2852
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
bit-parallel systolic multiplierfinite fieldirreducible trinomial
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