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Keyword : interconnection delay

A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2911-2924 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, multiple-bitwidth, distributed-register architecture, operation chaining, interconnection delay, floorplan,
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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 ; pp. 1439-1451 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, delay variation, body biasing, interconnection delay, floorplan,
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A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1278-1293 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, process variation, interconnection delay, distributed-register architecture, scenario,
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Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1294-1310 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan,
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An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 ; pp. 1376-1391 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, energy-optimization, interconnection delay, multiple clock domains,
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A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 ; pp. 1366-1375 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, RDR architecture, interconnection delay, operation chaining, floorplan,
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A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 ; pp. 1392-1405 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis (HLS), FPGA, floorplan, interconnection delay, MUX,
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Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 ; pp. 2597-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, interconnection delay, energy-optimization, dynamic multiple supply voltages,
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Prospects of Multiple-Valued VLSI Processors Takahiro HANYU Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 ; pp. 383-392 Type of Manuscript: INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: submicron VLSI, interconnection delay, multiple-valued hardware algorithm, parallel VLSI processor, MVL arithmetic and logic circuits,
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