Keyword : interconnect


A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing
Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/08/01
Vol. E97-A  No. 8 ; pp. 1688-1698
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Electron Beam Direct WritingCharacter ProjectionroutinginterconnectVIA
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High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2458-2466
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
electron beam direct writingcharacter projectionVIAinterconnectrouting
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A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations
Susumu KOBAYASHI Fumihiro MINAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1980-1985
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
clock skewinterconnectprocess variationsignal delay
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TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC
Hung Viet NGUYEN Myunghwan RYU Youngmin KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12 ; pp. 1864-1871
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
3D ICTSV (Through Silicon Via)powerdelayoptimizationinterconnectrepeater
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A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects
Jongsun KIM Gyungsu BYUN M. Frank CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5 ; pp. 854-857
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectcommunicationRF interconnectwire line transceiverVLSI
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Prediction of Self-Heating in Short Intra-Block Wires
Ken-ichi SHINKAI Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/03/01
Vol. E93-A  No. 3 ; pp. 583-594
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
self-heatingtemperatureinterconnectlocal wireprocess scaling
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Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 388-392
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectdelay variationparasitic resistancethermaltemperatureself-heatSoC
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Proximity Coupled Interconnect Using Broadside Coupled Composite Right/Left-Handed Transmission Line
Naobumi MICHISHITA Akiyoshi ABE Yoshihide YAMADA Anthony LAI Tatsuo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/09/01
Vol. E92-C  No. 9 ; pp. 1150-1156
Type of Manuscript:  Special Section PAPER (Special Section on Recent Progress in Microwave and Millimeter-Wave Technologies and Their Applications)
Category: 
Keyword: 
interconnectcomposite right/left-handed transmission linezeroth order resonancebroadside coupling
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Accurate Modeling Method for Cu Interconnect
Kenta YAMADA Hiroshi KITAHARA Yoshihiko ASAI Hideo SAKAMOTO Norio OKADA Makoto YASUDA Noriaki ODA Michio SAKURAI Masayuki HIROI Toshiyuki TAKEWAKI Sadayuki OHNISHI Manabu IGUCHI Hiroyasu MINDA Mieko SUZUKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6 ; pp. 968-977
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
Cuinterconnectcross-sectionmodeling
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Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
Kenta YAMADA Noriaki ODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 562-570
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
statisticalcorner conditionsinterconnectLPEdelay
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Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation
Noriaki ODA Hironori IMURA Naoyoshi KAWAHARA Masayoshi TAGAMI Hiroyuki KUNISHIMA Shuji SONE Sadayuki OHNISHI Kenta YAMADA Yumi KAKUHARA Makoto SEKINE Yoshihiro HAYASHI Kazuyoshi UENO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 848-855
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Device
Keyword: 
copperlow-kCMOSinterconnectdesignapplication
 Summary | Full Text:PDF

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3560-3568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
substrateinterconnectresistanceinductanceSoC
 Summary | Full Text:PDF

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3666-3670
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
interconnectdelay variationparasitic capacitanceSoC
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Carbon Nanotube Technologies for LSI via Interconnects
Yuji AWANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1499-1503
Type of Manuscript:  INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
carbon nanotubeinterconnectCVDnanotechnology
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MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm
Chia-Chi CHU Ming-Hong LAI Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 792-802
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
rational Arnoldi algorithmglobal Arnoldi algorithmsmodel reductionsinterconnectKrylov subspaceMIMO
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RF Passive Components Using Metal Line on Si CMOS
Kazuya MASU Kenichi OKADA Hiroyuki ITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 681-691
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
Si CMOSon-chip passiveinterconnecttransmission lineinductorvariable inductorreconfigurable RF circuit
 Summary | Full Text:PDF

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills
Atsushi KUROKAWA Akira KASEBE Toshiki KANAMOTO Yun YANG Zhangcai HUANG Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 847-855
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
dummy fillcapacitance extractioncapacitance formulainterconnect
 Summary | Full Text:PDF

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays
Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 856-864
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
interconnectworst-case delaystatic timing analysisprocess variationcapacitance extraction
 Summary | Full Text:PDF

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model
Hidenari NAKASHIMA Junpei INOUE Kenichi OKADA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3358-3366
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
interconnectlayout compactionphysical designplacementcore utilization
 Summary | Full Text:PDF

A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Toshiki KANAMOTO Tetsuya WATANABE Mitsutoshi SHIROTA Masayuki TERAI Tatsuya KUNIKIYO Kiyoshi ISHIKAWA Yoshihide AJIOKA Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3463-3470
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
SoCinterconnectphysical parameterlow-kcapacitanceresistancelayout parasitic extraction
 Summary | Full Text:PDF

Timing-Driven Placement Based on Path Topology Analysis
Feng CHENG Junfa MAO Xiaochun LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/08/01
Vol. E88-A  No. 8 ; pp. 2227-2230
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
timing-driven placementinterconnectdelaycritical path
 Summary | Full Text:PDF

A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula
Hideki SHIMA Toshimasa MATSUOKA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5 ; pp. 824-828
Type of Manuscript:  Special Section PAPER (Special Section on Microelectronic Test Structures)
Category: 
Keyword: 
spiral inductorsinterconnectclosed-form expressioninductance extractionanalytical technique
 Summary | Full Text:PDF

Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions
Chia-Chi CHU Herng-Jer LEE Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/02/01
Vol. E88-A  No. 2 ; pp. 533-537
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
interconnectmodel reductionsArnordi iterationsresidual error
 Summary | Full Text:PDF

Investigations of Optimum Tier Architectures for ASICs
Kan TAKEUCHI Kazumasa YANAGISAWA Kazuko SAKAMOTO Teruya TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/11/01
Vol. E87-A  No. 11 ; pp. 2983-2989
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
packing efficiencyinterconnectRent's ruleASICs
 Summary | Full Text:PDF

Efficient Routing of Board-Level Optical Clocks for Ultra High-Speed Systems
Chung-Seok (Andy) SEO Abhijit CHATTERJEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6 ; pp. 1310-1317
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category: 
Keyword: 
clockoptical waveguideinterconnectphysical designoptimization
 Summary | Full Text:PDF

Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays
Sadahiro TANI Yoshihiro UCHIDA Makoto FURUIE Shuji TSUKIYAMA BuYeol LEE Shuji NISHI Yasushi KUBOTA Isao SHIRAKAWA Shigeki IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 2923-2932
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
interconnectLCDparasitic capacitancesignal integritycircuit simulation
 Summary | Full Text:PDF

Representative Frequency for Interconnect R(f)L(f)C Extraction
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 2942-2951
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
interconnectextractionfrequency-dependent
 Summary | Full Text:PDF

Routing Methodology for Minimizing Crosstalk in SoC
Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/09/01
Vol. E86-A  No. 9 ; pp. 2347-2356
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCsignal integritycrosstalkinterconnecttiming analysis
 Summary | Full Text:PDF

Superconnect Technology
Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/12/01
Vol. E84-C  No. 12 ; pp. 1709-1716
Type of Manuscript:  INVITED PAPER (Special Issue on Integrated Systems with New Concepts)
Category: 
Keyword: 
system-on-a-chipsystem-in-a-packagesuperconnectRC delayinterconnect
 Summary | Full Text:PDF

Innovative Packaging and Fabrication Concept for a 28 GHz Communication Front-End
Wolfgang MENZEL Jurgen KASSNER Uhland GOEBEL 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/11/25
Vol. E82-C  No. 11 ; pp. 2021-2028
Type of Manuscript:  INVITED PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century)
Category: RF Assembly Technology
Keyword: 
packaginginterconnectfabrication techniquesplastic injection moldingwaveguide filters
 Summary | Full Text:PDF

Non-uniform Multi-Layer IC Interconnect Transmission Line Characterization for Fast Signal Transient Simulation of High-Speed/High-Density VLSI Circuits
Woojin JIN Hanjong YOO Yungseon EO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6 ; pp. 955-966
Type of Manuscript:  Special Section PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
interconnectsubstrate effectshielding effectsignal integritysignal delaycrosstalk noise
 Summary | Full Text:PDF

A Design Hierarchy of IC Interconnects and Gate Patterns
Shinji ODANAKA Akio MISAKA Kyoji YAMASHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6 ; pp. 948-954
Type of Manuscript:  INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
TCADinterconnectOPCgate patterndesign rule
 Summary | Full Text:PDF

Ribbon-Wire Interconnect Using Parasitic Element
Hajime IZUMI Hiroyuki ARAI Tatsuo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 662-664
Type of Manuscript:  LETTER
Category: Microwave and Millimeter Wave Technology
Keyword: 
ribbon-wire bondinginterconnectDC-breakparasitic elementelectromagnetic couplingFDTD method
 Summary | Full Text:PDF

Inlaid Cu Interconnects Employing Ti-Si-N Barrier Metal for ULSI Applications
Tadashi IIJIMA Yoshiaki SHIMOOKA Kyoichi SUGURO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4 ; pp. 568-572
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
CuTi-Si-Nbarrierinterconnect
 Summary | Full Text:PDF

An Analytical Modeling of Three Primary Wiring Capacitance Components for Multi-Layer Interconnect Structure
Susumu KUROSAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1793-1798
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
capacitancemodelinginterconnectLSILPE
 Summary | Full Text:PDF