Keyword : interconnect testing

Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip
Katherine Shu-Min LI Chih-Yun PAI Liang-Bi CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2649-2658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
interconnect fault toleranceinterconnect testinginterconnect diagnosisinterconnect resilienceoscillation ring scheme
 Summary | Full Text:PDF(1.9MB)

A Structured Walking-1 Approach for the Diagnosis of Interconnects and FPICs*
Tong LIU Fabrizio LOMBARDI Susumu HORIGUCHI Jung Hwan KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/01/25
Vol. E79-D  No. 1 ; pp. 29-40
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
interconnect testingFPIC testingdiagnosissyndrome
 Summary | Full Text:PDF(1001.5KB)