Keyword : integer linear programming


A Petri Net Approach to Generate Integer Linear Programming Problems
Morikazu NAKAMURA Takeshi TENGAN Takeo YOSHIDA 
Publication:   
Publication Date: 2019/02/01
Vol. E102-A  No. 2 ; pp. 389-398
Type of Manuscript:  Special Section PAPER (Special Section on Mathematical Systems Science and its Applications)
Category: 
Keyword: 
mathematical programminginteger linear programmingPetri netcolored timed Petri netautonomous Petri net
 Summary | Full Text:PDF(1.3MB)

Cloud Provider Selection Models for Cloud Storage Services to Satisfy Availability Requirements
Eiji OKI Ryoma KANEKO Nattapong KITSUWAN Takashi KURIMOTO Shigeo URUSHIDANI 
Publication:   
Publication Date: 2017/08/01
Vol. E100-B  No. 8 ; pp. 1406-1418
Type of Manuscript:  PAPER
Category: Network
Keyword: 
cloud storageavailabilityservice requirementoptimizationinteger linear programming
 Summary | Full Text:PDF(3.4MB)

Static Mapping of Parallelizable Tasks under Deadline Constraints
Yining XU Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1500-1502
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
task mappingmanycore embedded systemsinteger linear programming
 Summary | Full Text:PDF(326.1KB)

Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems
Tsutomu INAMOTO Yoshinobu HIGAMI Shin-ya KOBAYASHI 
Publication:   
Publication Date: 2017/02/01
Vol. E100-A  No. 2 ; pp. 385-394
Type of Manuscript:  Special Section PAPER (Special Section on Mathematical Systems Science and its Applications)
Category: 
Keyword: 
elevator operation problemmulti-car elevator systeminteger linear programminginterference prevention
 Summary | Full Text:PDF(1MB)

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework
Junki KAWAGUCHI Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1366-1373
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
general-synchronous frameworktechnology mappinginteger linear programming
 Summary | Full Text:PDF(753.4KB)

Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing
Junghoon OH Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1311-1322
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
speculative resource sharingsoft-errorfault tolerant datapathtriple algorithm redundancyhigh-level synthesisinteger linear programming
 Summary | Full Text:PDF(1.2MB)

Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems
Yining XU Yang LIU Junya KAIDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1417-1419
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
application mappingmanycore embedded systemsinteger linear programming
 Summary | Full Text:PDF(442.5KB)

Optimum Route Design in 1+1 Protection with Network Coding for Instantaneous Recovery
Abu Hena Al MUKTADIR Eiji OKI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2014/01/01
Vol. E97-B  No. 1 ; pp. 87-104
Type of Manuscript:  PAPER
Category: Internet
Keyword: 
routingnetwork coding1+1 protectioninteger linear programmingheuristic algorithm
 Summary | Full Text:PDF(1.7MB)

An Exact Approach for GPC-Based Compressor Tree Synthesis
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2553-2560
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
compressor treegeneralized parallel counterinteger linear programmingarithmetic synthesis
 Summary | Full Text:PDF(850.4KB)

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2563-2570
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
asynchronous on-chip interconnectCHAINstuck-at faulttest schedulinginteger linear programming
 Summary | Full Text:PDF(1.3MB)

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits
Hsin-Hsiung HUANG Jui-Hung HUNG Cheng-Chiang LIN Tsai-Ming HSIEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11 ; pp. 2402-2411
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
analog circuitswire planning with obstacleselectromigrationinterferenceinteger linear programming
 Summary | Full Text:PDF(1.3MB)

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/04/01
Vol. E94-A  No. 4 ; pp. 1067-1081
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
datapath synthesisdelay variationregister assignmenthold timing constraintbackward-data-direction clockinginteger linear programming
 Summary | Full Text:PDF(589.9KB)

Optimal Supply Voltage Assignment under Timing, Power and Area Constraints
Hsi-An CHIEN Cheng-Chiang LIN Hsin-Hsiung HUANG Tsai-Ming HSIEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/04/01
Vol. E93-A  No. 4 ; pp. 761-768
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
level shiftermultiple supply voltagelow powervoltage assignmentinteger linear programming
 Summary | Full Text:PDF(1MB)

Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming
Ki-Yong AHN Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9 ; pp. 2318-2325
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
system on chiplow power designpartitioninginteger linear programming
 Summary | Full Text:PDF(380.5KB)

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1096-1105
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
datapath synthesisdelay variationregister assignmentsetup and hold constraintsminimum delay compensationinteger linear programming
 Summary | Full Text:PDF(347.8KB)

Optimization for Optical Network Designs Based on Existing Power Grids
Areeyata SRIPETCH Poompat SAENGUDOMLERT 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/03/01
Vol. E91-B  No. 3 ; pp. 689-699
Type of Manuscript:  PAPER
Category: Optical Fiber for Communications
Keyword: 
physical topology designrouting and wavelength assignmentoptical amplifier placementinteger linear programmingsimulated annealing
 Summary | Full Text:PDF(1.3MB)

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
Shih-Hsu HUANG Chun-Hua CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1 ; pp. 375-382
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high-level synthesisinteger linear programmingschedulinglow power
 Summary | Full Text:PDF(231KB)

A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units
Tsuyoshi SADAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4 ; pp. 792-799
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high-level synthesisschedulingallocationmodule selectionoperation chaininginteger linear programming
 Summary | Full Text:PDF(215.1KB)

An ILP Approach to the Slack Driven Scheduling Problem
Shih-Hsu HUANG Chun-Hua CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6 ; pp. 1852-1858
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
high-level synthesisinteger linear programmingschedulingslack optimization
 Summary | Full Text:PDF(209.5KB)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment
Makoto SUGIHARA Taiga TAKATA Kenta NAKAMURA Ryoichi INANAMI Hiroaki HAYASHI Katsumi KISHIMOTO Tetsuya HASEBE Yukihiro KAWANO Yusuke MATSUNAGA Kazuaki MURAKAMI Katsuya OKUMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 377-383
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: CAD
Keyword: 
cell librarycharacter projectionelectron beamEB shotsthroughputoptimizationinteger linear programming
 Summary | Full Text:PDF(427.7KB)

Analysis and Design of Multicast Routing and Wavelength Assignment in Mesh and Multi-Ring WDM Transport Networks with Multiple Fiber Systems
Charoenchai BOWORNTUMMARAT Lunchakorn WUTTISITTIKULKIJ Sak SEGKHOONTHOD 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2004/11/01
Vol. E87-B  No. 11 ; pp. 3216-3229
Type of Manuscript:  PAPER
Category: Network
Keyword: 
multicast routing and wavelength assignmentmesh designmulti-ring designlight-treefanoutinteger linear programminglower boundnetwork connectivity
 Summary | Full Text:PDF(1.7MB)

Resource-Optimal Software Pipelining Using Flow Graphs
Dirk FIMMEL Jan MULLER Renate MERKER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/09/01
Vol. E86-D  No. 9 ; pp. 1560-1568
Type of Manuscript:  INVITED PAPER (Special Issue on Parallel and Distributed Computing, Applications and Technologies)
Category: Software Systems and Technologies
Keyword: 
software pipelininginstruction level parallelisminteger linear programmingresource constraintsheterogeneous architectures
 Summary | Full Text:PDF(460.1KB)

Design of Reconfigurable Lightpaths in IP over WDM Networks
Hiroaki HARAI Fumito KUBOTA Hidenori NAKAZATO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2000/10/25
Vol. E83-B  No. 10 ; pp. 2234-2244
Type of Manuscript:  Special Section PAPER (Special Issue on Advanced Internetworking based on Photonic Network Technologies)
Category: 
Keyword: 
IP over WDM networknetwork designlightpath configurationinteger linear programmingMPLS
 Summary | Full Text:PDF(763.7KB)

ILIN: An Implementation of the Integer Labeling Algorithm for Integer Programming
Qiang LI Fred JANSSEN Zaifu YANG Tetsuo IDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2 ; pp. 304-309
Type of Manuscript:  PAPER
Category: Numerical Analysis and Optimization
Keyword: 
simplexinteger pointinteger labeling algorithminteger linear programming
 Summary | Full Text:PDF(557.7KB)

An Optimal Block Terminal Assignment Algorithm for VLSI Data Path Allocation
Shoichiro YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 564-566
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
block terminal assignmentdata path allocationhigh-level synthesisinteger linear programming
 Summary | Full Text:PDF(221.9KB)

A Scheduling Method Using Boolean Equations in High-Level Synthesis
Toshiaki MIYAZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12 ; pp. 1728-1731
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category: 
Keyword: 
integer linear programmingBDDdata path
 Summary | Full Text:PDF(332.3KB)