Keyword : instruction-level parallelism


Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control
Hideki ANDO Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Vol. E99-D  No. 2 ; pp. 341-350
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processormemory-level parallelisminstruction-level parallelismpower consumption
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MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism
Yuya KORA Kyohei YAMAGUCHI Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12 ; pp. 3110-3123
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processormemory-level parallelisminstruction-level parallelism
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System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method
Hak-Jun KIM Sun-Mo KIM Sang-Bang CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/25
Vol. E82-A  No. 6 ; pp. 927-938
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))
Category: 
Keyword: 
superscalar processorinstruction-level parallelismin-order issueout-of-order issueinstruction windowreorder bufferqueuing model
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