Keyword : instruction scheduling

A New Approach to Embedded Software Optimization Based on Reverse Engineering
Nguyen Ngoc BINH Pham Van HUONG Bui Ngoc HAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/06/01
Vol. E98-D  No. 6 ; pp. 1166-1175
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
embedded software optimization, reverse engineering, power consumption, performance, instruction scheduling, genetic algorithm, 
 Summary | Full Text:PDF
A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems
Sung-Rae LEE Ser-Hoon LEE Sun-Young HWANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2162-2171
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
embedded system, low-power, instruction scheduling, recoding, 
 Summary | Full Text:PDF
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3258-3267
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
partial forwarding, instruction scheduling, compiler, design space exploration, 
 Summary | Full Text:PDF
A Low-Power Instruction Issue Queue for Microprocessors
Shingo WATANABE Akihiro CHIYONOBU Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 400-409
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
microprocessors, instruction scheduling, CAM, RAM, low-power, 
 Summary | Full Text:PDF
Parallelism-Independent Scheduling Method
Kirilka NIKOLOVA Atusi MAEDA Masahiro SOWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1138-1150
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
instruction scheduling, static scheduling algorithms, multiprocessor scheduling, degree of parallelism (DOP), directed acyclic graphs (DAGs), 
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Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2621-2629
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
compiler optimization, instruction scheduling, low power, caches, 
 Summary | Full Text:PDF