Keyword : instruction level parallelism


Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation
Yukinori SATO Ken-ichi SUZUKI Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/03/01
Vol. E90-D  No. 3 ; pp. 627-636
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
clustered architecturepartitioned register filesnon-consistent register filesinstruction level parallelism
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A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors
Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12 ; pp. 2508-2516
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Dependable Systems
Keyword: 
fault-tolerancetime redundancytransient faultsinstruction level parallelisminstruction reissue
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Resource-Optimal Software Pipelining Using Flow Graphs
Dirk FIMMEL Jan MULLER Renate MERKER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/09/01
Vol. E86-D  No. 9 ; pp. 1560-1568
Type of Manuscript:  INVITED PAPER (Special Issue on Parallel and Distributed Computing, Applications and Technologies)
Category: Software Systems and Technologies
Keyword: 
software pipelininginstruction level parallelisminteger linear programmingresource constraintsheterogeneous architectures
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Potential of Constructive Timing-Violation
Toshinori SATO Itsujiro ARITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 323-330
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
instruction level parallelismlow power designfault tolerancetiming constraintsspeculative execution
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Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Shinsuke KOBAYASHI Yoshinori TAKEUCHI Akira KITAJIMA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3 ; pp. 748-754
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
multi-threadingvery long instruction word (VLIW)instruction level parallelismthread level parallelismHW/SW co-design
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A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories
Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1398-1407
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
instruction level parallelismsuperscalar processorsout-of-order executionnon-consecutive basic block bufferdynamic speculation of data dependence
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