Keyword : implication


On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques
Fu-Shing CHIM Tak-Kei LAM Yu-Liang WU Hongbing FAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2853-2865
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design automationATPGimplicationredundancy identificationgraph-based rewiringvery-large-scale integration
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Multi-Cycle Path Detection for Sequential Circuits and Its Application to Real Designs
Hiroyuki HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3176-3183
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
multi-cycle pathfalse pathsequential circuitimplicationATPGmultiple clock
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On Processing Order for Obtaining Implication Relations in Static Learning
Hideyuki ICHIHARA Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10 ; pp. 1908-1911
Type of Manuscript:  LETTER
Category: Fault Tolerance
Keyword: 
test generationimplicationstatic learning
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Logic Minimization for Large-Scale Networks Based on Multi-Signal Implications
Masayuki YUGUCHI Kazutoshi WAKABAYASHI Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2390-2397
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesislogic minimizationimplicationimplication graph
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Logic Optimization: Redundancy Addition and Removal Using Implication Relations
Hideyuki ICHIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 724-730
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword: 
logic optimizationimplicationredundancy identification
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