Keyword : high-speed DAC


Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit
Masayuki UNO Shoji KAWAHITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 702-709
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
charge-redistribution DACsmall-offset DAClow power DAChigh-speed DACflip-around sample-and-hold circuit (S/H)
 Summary | Full Text:PDF(407.5KB)

The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR Characteristics for the 90 MHz Output Signal
Hiroki SAKURAI Yasuhiro SUGIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/06/01
Vol. E86-C  No. 6 ; pp. 1077-1084
Type of Manuscript:  Special Section PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
Category: 
Keyword: 
high-speed DAClow-voltage DAChigh-resolution DACCMOS DACSFDR characteristics
 Summary | Full Text:PDF(616.9KB)