IEICE Trans

Keyword : high-level synthesis

Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis Saya OHIRA Naoki TSUCHIYA Tetsuya MATSUMURA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 ; pp. 1804-1812 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: sound processer, super-directional sound, ultrasound, high-level synthesis, FPGA,
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A Describing Method of an Image Processing Software in C for a High-Level Synthesis Considering a Function Chaining Akira YAMAWAKI Seiichi SERIKAWA
Publication: Publication Date: 2018/02/01 Vol. E101-D No. 2 ; pp. 324-334 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology and Platform Keyword: high-level synthesis, FPGA, describing method, image processing, function chaining,
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A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2911-2924 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, multiple-bitwidth, distributed-register architecture, operation chaining, interconnection delay, floorplan,
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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 ; pp. 1439-1451 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, delay variation, body biasing, interconnection delay, floorplan,
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Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing Junghoon OH Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1311-1322 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: speculative resource sharing, soft-error, fault tolerant datapath, triple algorithm redundancy, high-level synthesis, integer linear programming,
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A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1278-1293 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, process variation, interconnection delay, distributed-register architecture, scenario,
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An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 ; pp. 1376-1391 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, energy-optimization, interconnection delay, multiple clock domains,
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A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 ; pp. 1366-1375 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, RDR architecture, interconnection delay, operation chaining, floorplan,
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Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration Keisuke DOHI Koji OKINA Rie SOEJIMA Yuichiro SHIBATA Kiyoshi OGURI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/02/01 Vol. E98-D No. 2 ; pp. 298-308 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Application Keyword: high-level synthesis, FPGA, stencil computation, heat conduction simulation,
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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis Akihiro SUDA Hideki TAKASE Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2498-2506 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, array partitioning, buffer management, Polyhedral Optimization,
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An Energy-Efficient Patchable Accelerator and Its Design Methods Hiroaki YOSHIDA Masayuki WAKIZAKA Shigeru YAMASHITA Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2507-2517 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: engineering change, high-level synthesis, energy efficiency,
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Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis Nan WANG Song CHEN Wei ZHONG Nan LIU Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/08/01 Vol. E97-A No. 8 ; pp. 1709-1719 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: mobility overlap removal, dual-V_th, leakage power, register usage, high-level synthesis,
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Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 ; pp. 2597-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, interconnection delay, energy-optimization, dynamic multiple supply voltages,
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Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle Keisuke INOUE Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 ; pp. 2689-2697 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dual-edge-triggered flip-flop, programmable duty cycle, operation scheduling, MILP, high-level synthesis,
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Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches Keisuke INOUE Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/08/01 Vol. E96-A No. 8 ; pp. 1712-1722 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: flip-flop/latch-based design, high-level synthesis, resource binding, storage-type selection,
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A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/01/01 Vol. E96-A No. 1 ; pp. 312-321 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, RDR, thermal-aware, hot spots, interconnect delays,
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A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths Keisuke INOUE Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2330-2337 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: clock-skew, ordered clocking, high-level synthesis,
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Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor Takao TOI Takumi OKAMOTO Toru AWASHIMA Kazutoshi WAKABAYASHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2619-2627 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: coarse-grained reconfigurable architecture, dynamically reconfigurable processor, high-level synthesis, iterative synthesis, wire delay,
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A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication Chia-I CHEN Juinn-Dar HUANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 ; pp. 1300-1308 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: multicycle communication, architectural synthesis, high-level synthesis, performance-driven, criticality-driven,
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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures Akira OHCHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3169-3179 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, floorplan, distributed-register architecture, generalized distributed-register architecture, local register, local controller,
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Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath Tasuku NISHIHARA Takeshi MATSUMOTO Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 ; pp. 972-984 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Hardware Verification Keyword: high-level synthesis, behavioral synthesis, formal verification, equivalence checking,
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Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3596-3606 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, low power, interconnection network, genetic algorithm,
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High-Level Synthesis of Software Function Calls Masanari NISHIMURA Nagisa ISHIURA Yoshiyuki ISHIMORI Hiroyuki KANBARA Hiroyuki TOMIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3556-3558 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, CCAP, hardware/software co-design, C-based design,
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Memory Allocation for Multi-Resolution Image Processing Yasuhiro KOBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/10/01 Vol. E91-D No. 10 ; pp. 2386-2397 Type of Manuscript: PAPER Category: VLSI Systems Keyword: high-level synthesis, interconnection-aware architecture, stereo vision,
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An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management Shih-Hsu HUANG Chun-Hua CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 ; pp. 375-382 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, integer linear programming, scheduling, low power,
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Max-Flow Scheduling in High-Level Synthesis Liangwei GE Song CHEN Kazutoshi WAKABAYASHI Takashi TAKENAKA Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/09/01 Vol. E90-A No. 9 ; pp. 1940-1948 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: scheduling, high-level synthesis, power-ground integrity,
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A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units Tsuyoshi SADAKATA Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 ; pp. 792-799 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: high-level synthesis, scheduling, allocation, module selection, operation chaining, integer linear programming,
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Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 ; pp. 3427-3434 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: HDL, high-level synthesis, bit-length optimization, non-linear programming,
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An ILP Approach to the Slack Driven Scheduling Problem Shih-Hsu HUANG Chun-Hua CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/06/01 Vol. E89-A No. 6 ; pp. 1852-1858 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, integer linear programming, scheduling, slack optimization,
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On Multiple-Voltage High-Level Synthesis Using Algorithmic Transformations Lan-Rong DUNG Hsueh-Chih YANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3100-3108 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: multiple voltage scheduling, low-power circuit, loop shrinking, retiming, unfolding, high-level synthesis,
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High-Level Power Optimization Based on Thread Partitioning Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3075-3082 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: high-level synthesis, low power, thread partitioning, gated clocks,
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Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3184-3191 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic and High Level Synthesis Keyword: HDL, high-level synthesis, parallelizing compiler, bit length,
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High-Level Synthesis by Ants on a Tree Rachaporn KEINPRASIT Prabhas CHONGSTITVATANA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/10/01 Vol. E86-A No. 10 ; pp. 2659-2669 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: ant algorithms, high-level synthesis, data path design, genetic algorithms, dynamic niche sharing,
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A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2655-2666 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High Level Synthesis Keyword: high-level synthesis, energy optimization, area/time constraints,
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High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 ; pp. 827-834 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: high-level synthesis, power estimation, gated clock, switching activity, sequential circuit,
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An RTL Design-Space Exploration Method for High-Level Applications Peng-Cheng KAO Chih-Kuang HSIEH Ching-Feng SU Allen C.-H. WU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2648-2654 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High Level Synthesis Keyword: design exploration, high-level synthesis, RTL, design space, AT-curve,
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An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares Nozomu TOGAWA Masayuki IENAGA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/05/01 Vol. E84-A No. 5 ; pp. 1166-1176 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: high-level synthesis, control-based hardware, area/time optimization, scheduling, resource allocation,
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CAM Processor Synthesis Based on Behavioral Descriptions Nozomu TOGAWA Tatsuhiko WAKUI Tatsuhiko YODEN Makoto TERAJIMA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2464-2473 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design and High-level Synthesis Keyword: content addressable memory, functional memory, behavioral synthesis, behavioral description, high-level synthesis,
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Hardware Synthesis from C Programs with Estimation of Bit Length of Variables Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 ; pp. 2338-2346 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, hardware/software codesign, VHDL, C language, compiler,
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A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement Taewhan KIM Ki-Seok CHUNG C. L. LIU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/06/25 Vol. E82-A No. 6 ; pp. 1070-1081 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, testability, scheduling,
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A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration Nozomu TOGAWA Takafumi HISAKI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 ; pp. 2563-2575 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-level Synthesis Keyword: data-flow oriented process, high-level synthesis, data-flow graph enumeration, scheduling, resource binding,
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Module Selection Using Manufacturing Information Hiroyuki TOMIYAMA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 ; pp. 2576-2584 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-level Synthesis Keyword: high-level synthesis, module selection, manufacturability, yield,
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High-Level Synthesis for Weakly Testable Data Paths Michiko INOUE Kenji NODA Takeshi HIGASHIMURA Toshimitsu MASUZAWA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 ; pp. 645-653 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Test Synthesis Keyword: high-level synthesis, testability, sequential ATPG, non-scan design,
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A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/06/25 Vol. E81-A No. 6 ; pp. 1231-1241 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: scheduling, resource binding, high-level synthesis, data-flow graph, gradual time-frame reduction,
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An Overlapped Scheduling Method for an Iterative Processing Algorithm with Conditional Operations Kazuhito ITO Tatsuya KAWASAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 ; pp. 429-438 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: scheduling, high-level synthesis, digital signal processing, conditional branch, overlapped schedule,
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Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations Akihiro MATSUURA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 ; pp. 455-461 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: high-level synthesis, common subexpression elimination, linear transforms, matrix decomposition,
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A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem Akihiro MATSUURA Mitsuteru YUKISHITA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 ; pp. 1767-1773 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: constant multiplication, MCM problem, high-level synthesis, common subexpression,
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An Optimal Block Terminal Assignment Algorithm for VLSI Data Path Allocation Shoichiro YAMADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 ; pp. 564-566 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: block terminal assignment, data path allocation, high-level synthesis, integer linear programming,
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A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs Vasily G. MOSHNYAGA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/25 Vol. E79-D No. 10 ; pp. 1389-1395 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Synthesis Keyword: high-level synthesis, ASIC design methodology,
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Reclocking Controllers for Minimum Execution Time Pradip JHA Sri PARAMESWARAN Nikil DUTT
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 ; pp. 1715-1721 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: reclocking, high-level synthesis, design reuse,
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An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis Seong Yong OHM Fadi J. KURDAHI Chu Shik JHON
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 ; pp. 231-236 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Synthesis Keyword: high-level synthesis, scheduling, lower bound estimation,
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High-Level Synthesis --A Tutorial Allen C.-H. WU Youn-Long LIN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/03/25 Vol. E78-D No. 3 ; pp. 209-218 Type of Manuscript: INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Synthesis Keyword: high-level synthesis, design methodology, VLSI design, design automation,
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High-Level Synthesis of a Multithreaded Processor for Image Generation Takao ONOYE Toshihiro MASAKI Isao SHIRAKAWA Hiroaki HIRATA Kozo KIMURA Shigeo ASAHARA Takayuki SAGISHIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/25 Vol. E78-A No. 3 ; pp. 322-330 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: processor, multithread, parallel processing, high-level synthesis, image generation,
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Datapath Scheduling for Behavioral Description with Conditional Branches Akihisa YAMADA Toshiki YAMAZAKI Nagisa ISHIURA Isao SHIRAKAWA Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 ; pp. 1999-2009 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, datapath scheduling, 0-1 integer programming problem, binary decision diagram, branch-and-bound method,
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High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems Yasuaki SAWANO Bumchul KIM Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/25 Vol. E77-C No. 7 ; pp. 1101-1107 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: intelligent integrated systems, high-level synthesis, parallel processing, minimum latency, scheduling,
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A Mathematical Formulation of Allocation and Floorplanning Problem in VLSI Data Path Synthesis Shoichiro YAMADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/06/25 Vol. E77-A No. 6 ; pp. 1043-1049 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: high-level synthesis, data path allocation, floorplanning, mixed integer linear programming,
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High-Level Modeling and Synthesis of Communicating Processes Using VHDL Wayne WOLF Richard MANNO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1039-1046 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Design Keyword: high-level synthesis, VHDL, control-dominated systems,
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Functional Design of a Special Purpose Processor Based on High Level Specification Description Hironobu KITABATAKE Katsuhiko SHIRAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 ; pp. 1182-1190 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, ASIC design, VHDL,
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Optimizing and Scheduling DSP Programs for High Performance VLSI Designs Frederico Buchholz MACIEL Yoshikazu MIYANAGA Koji TOCHINAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 ; pp. 1191-1201 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, optimization, retiming, iteration bound, scheduling,
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New Trend and Future Issues of Hardware Description Language and High-Level Synthesis Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 ; pp. 307-313 Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: HDL, high-level synthesis, VHDL, verilog HDL, UDL/I, PARTHENON, SFL,
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