Keyword : high speed SRAM, low power


111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method
Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 735-742
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
memorysynchronous SRAMhigh speed SRAM, low powerclock
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