Keyword : hierarchical bit-line


A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
Isao NARITAKE Tadahiko SUGIBAYASHI Satoshi UTSUGI Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 787-791
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memoryDRAMhierarchical bit-linerefresh
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