Keyword : hierarchical I/O design

µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO Hiroyuki MIZUNO Nobuhiro OODAIRA Yoshihiko YASU Kazumasa YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 589-597
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
low-costSystem-on-ChipSoCSystem-in-PackageSiPhierarchical I/O designsignal-level convertersignal wall functionlow-powerinterconnect circuit
 Summary | Full Text:PDF(967.2KB)